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(fttx-pool-157.180.225.81.bambit.de [157.180.225.81]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id 06C8B1226F1; Fri, 20 Jun 2025 08:36:13 +0000 (UTC) From: Frank Wunderlich To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH v5 07/13] arm64: dts: mediatek: mt7988: add switch node Date: Fri, 20 Jun 2025 10:35:38 +0200 Message-ID: <20250620083555.6886-8-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250620083555.6886-1-linux@fw-web.de> References: <20250620083555.6886-1-linux@fw-web.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250620_013618_821714_FAFD7FBB X-CRM114-Status: UNSURE ( 9.69 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Landen Chao , Sean Wang , =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , netdev@vger.kernel.org, linux-pm@vger.kernel.org, Daniel Golle , linux-kernel@vger.kernel.org, DENG Qingfang , Johnson Wang , linux-mediatek@lists.infradead.org, Jia-Wei Chang , Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, Felix Fietkau Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Frank Wunderlich Add mt7988 builtin mt753x switch nodes. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich --- v4: - drop phy-mode for gsw-phy - reorder phy-mode after phy-handle - drop interrupt parent from switch v2: - drop labels and led-function too (have to be in board) --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 148 ++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 3ab77ad4736a..33a80199ffbe 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -742,6 +742,154 @@ ethsys: clock-controller@15000000 { #reset-cells = <1>; }; + switch: switch@15020000 { + compatible = "mediatek,mt7988-switch"; + reg = <0 0x15020000 0 0x8000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = ; + resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + gsw_port0: port@0 { + reg = <0>; + phy-handle = <&gsw_phy0>; + phy-mode = "internal"; + }; + + gsw_port1: port@1 { + reg = <1>; + phy-handle = <&gsw_phy1>; + phy-mode = "internal"; + }; + + gsw_port2: port@2 { + reg = <2>; + phy-handle = <&gsw_phy2>; + phy-mode = "internal"; + }; + + gsw_port3: port@3 { + reg = <3>; + phy-handle = <&gsw_phy3>; + phy-mode = "internal"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + mediatek,pio = <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupts = <0>; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy0_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupts = <1>; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy1_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy1_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + interrupts = <2>; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy2_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy2_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupts = <3>; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy3_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy3_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + }; + }; + ethwarp: clock-controller@15031000 { compatible = "mediatek,mt7988-ethwarp"; reg = <0 0x15031000 0 0x1000>; -- 2.43.0