From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E428C77B7F for ; Mon, 23 Jun 2025 11:45:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Lg0Gavc3fUjRIrYBtMLc6i2GZJBCntsf4mxvw9SYo7I=; b=zUlpfrhD2EGvLedMJx0QSXe68s 0VMNMVDiKG1sm9CNQ9EvaFlC41roRMIgs93jWqtWzBcM9BUBDdyH8qBo4SspMMOhXF1sM9mpb8WXA BLEPQYxTjcFdZruD2hhCBn/HEnvLDUimYtM0rJikCUEUSOqrf3RspnZmhuEtvZdsIyyeWiUwV9HQM s3tRz7PIuS3YsuLH6tcdm30sIFudpJbLChSlsqLM8LhbFTUJpCSI+lg+wctiPnSD7uJRSWXG0VAUo 2UEXL/NYFltx13QPQXwFk1JIcV9VuIhiGIWCdsNepdllvWdvp3R+A50B+v23MNPXaiqv7yYyuk6sM jhRNoKTg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uTfbr-00000002XiU-1LLJ; Mon, 23 Jun 2025 11:45:11 +0000 Received: from bali.collaboradmins.com ([2a01:4f8:201:9162::2]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uTeRZ-00000002M0R-0eGM; Mon, 23 Jun 2025 10:30:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750674627; bh=wNy7ArrNq1Aj4Z/u6XgdPtfGnfQ0qQj1ihgD7HUsJ/g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ddO/yesbUqWOAYqcVSZUDNJcNczqspnGF6RxG7IZ2A2+bBG7uweNvMM/SnysMwvsh bVcFikKc8i0jm60EBv8Z8xruOkUu5BYzoiYo/vzxemOuaukEhVEGXxMS3Lay6+M9C/ kQeAGBSZlveRLsJotJEO8ygpcK/4TzLUW+CudGAyZmDtMoFpFsLj7HOZPMHY+JOIxv QyKpS7oidPCmxr9cO2yT0p5AFpQ5w5kcbFN38fDRtL/JeIzHI0nIZOP4iVcZmhqqUk 7ufqsaiGaErFOeWkEZY/5JIkojgBB3PcqaDyJDBFGnSYTG0RcbyAMcTBb12+njCjml Ntw5GdtU1LBig== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:e046:b666:1d47:e832]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 699DD17E0FDB; Mon, 23 Jun 2025 12:30:26 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao Subject: [PATCH 01/30] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Date: Mon, 23 Jun 2025 12:29:11 +0200 Message-Id: <20250623102940.214269-2-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250623102940.214269-1-laura.nao@collabora.com> References: <20250623102940.214269-1-laura.nao@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250623_033029_337894_A88ADAAA X-CRM114-Status: UNSURE ( 9.54 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On MT8196, there are set/clr registers to control a shared PLL enable register. These are intended to prevent different masters from manipulating the PLLs independently. Add the corresponding en_set_reg and en_clr_reg fields to the mtk_pll_data structure. Signed-off-by: Laura Nao --- drivers/clk/mediatek/clk-pll.c | 4 ++++ drivers/clk/mediatek/clk-pll.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index ce453e1718e5..49ca25dd5418 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -308,6 +308,10 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, pll->en_addr = base + data->en_reg; else pll->en_addr = pll->base_addr + REG_CON0; + if (data->en_set_reg) + pll->en_set_addr = base + data->en_set_reg; + if (data->en_clr_reg) + pll->en_clr_addr = base + data->en_clr_reg; pll->hw.init = &init; pll->data = data; diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index 285c8db958b3..c4d06bb11516 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -47,6 +47,8 @@ struct mtk_pll_data { const struct mtk_pll_div_table *div_table; const char *parent_name; u32 en_reg; + u32 en_set_reg; + u32 en_clr_reg; u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ u8 pcw_chg_bit; }; @@ -68,6 +70,8 @@ struct mtk_clk_pll { void __iomem *pcw_addr; void __iomem *pcw_chg_addr; void __iomem *en_addr; + void __iomem *en_set_addr; + void __iomem *en_clr_addr; const struct mtk_pll_data *data; }; -- 2.39.5