From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF29AC77B7F for ; Mon, 23 Jun 2025 12:04:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=I2gs8XHZ0Ylm88GlPS5hYB+bjm5L7XSA5caFrtGferU=; b=DWxs2X/qFa97mUCC/W+a1NxAbb sQqQLNSDPSE5FEYnEY24fm4sQ3ufzPue0OF1H/pVR3nJw6K9vdVewpM5BOigp955bJ77WCn323m4T P+qr68YOxpMP1vJPS6tyKZazV7xN2GQyJt3makOFiZjnuVU5Y6co0NV1bcGWgN1IUs4Lfc5OTlCgv 5g2BqM2awtTQqxjvOhmLIHSYHH9ZYbmmiARtQp0idGrhnpflBZ03HWEQBqYO0Fq6qSKhZhSoDW4Du k/S0LtbrTGN+mSi6dP6+fBp4O/9wvLxoqR8UriRuczq1bIw/9QiOko6SKz7TOjus5A6WF4d8LHfaR ENiDQ/cQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uTfu6-00000002beT-1s5F; Mon, 23 Jun 2025 12:04:02 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uTeRz-00000002MB4-1tbN; Mon, 23 Jun 2025 10:30:55 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=I2gs8XHZ0Ylm88GlPS5hYB+bjm5L7XSA5caFrtGferU=; b=qGxK2gtjZtXH5BFmZJL6u3VmVD jfWD9MDsKxvUWZhMSXlh2Vi4zRvYLLnSvjd04FOSRBCDs3gjUuSky/MTKKEdY1DcS4+3N54xML8sD eH4ob0KyQwN1lvFNgFB7PiI7ZZnSbRYorlEBSfAJbh2X7O3iX76PO29FOi2GYmPzZuKlrg1pGL6Zs Q3ANuUVg2AgSRL8VIHZ9P0eU9O4Lhrr6w+Go4Zz3D0tWZxkev8e2jrougf2ULGTQ/ZuyfNcP+Sop0 S2JxrqfDDy8P3a/OcamKIvhWnfV3LV9TlX67GgYX3id2Ys8JPJWxHMAk+N7BEF5T074/ec58chFOC k3QZt8xw==; Received: from bali.collaboradmins.com ([2a01:4f8:201:9162::2]) by desiato.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uTeRw-00000005BYU-2fUf; Mon, 23 Jun 2025 10:30:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750674651; bh=HGB5hTdudqHPvZ2s2JmA0/yIpvQqwg0Mw/OonIslSng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AO/ZYx2xNHQ5tIvuoOi8KXV0kzgvdAfkxa2XV/yEGVxZ65zP9/z62iqKzjV9PDE6L TCVhlFvar67DVdySVJSFZWkVMLh+Br7euaNIPXnHLN7xEkySeN+aTgNSPi1eBPgNKI jBORwsBMqh1ZPr1UNTrykzizoeDVJDxasfvWWl6SLY93DPJ4sPWuXGXkk7hXXH/GLN /irHWKvY4uzgHiCEn/ekzl5eFkq9qCiG5PCmPZBXLp3krAY5zeplEKA20H5aAULQcn B0fV9XwdjqzMFWMmIeRyT7ZTYZFh3ECLgSI5SWiXP0+wGfV8Z/a2MiuSEFZom1lrAm D8BYc+GD+YyFw== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:e046:b666:1d47:e832]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 2EC7017E0342; Mon, 23 Jun 2025 12:30:50 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao Subject: [PATCH 19/30] clk: mediatek: Add MT8196 mcu clock support Date: Mon, 23 Jun 2025 12:29:29 +0200 Message-Id: <20250623102940.214269-20-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250623102940.214269-1-laura.nao@collabora.com> References: <20250623102940.214269-1-laura.nao@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250623_113052_860201_F85D6001 X-CRM114-Status: GOOD ( 17.54 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add support for the MT8196 mcu clock controller, which provides PLL control for MCU. Signed-off-by: Laura Nao --- drivers/clk/mediatek/Kconfig | 7 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8196-mcu.c | 166 ++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8196-mcu.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 6c556bec4531..ed1073c5b432 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -1082,6 +1082,13 @@ config COMMON_CLK_MT8196_IMP_IIC_WRAP help This driver supports MediaTek MT8196 i2c clocks. +config COMMON_CLK_MT8196_MCUSYS + tristate "Clock driver for MediaTek MT8196 mcusys" + depends on COMMON_CLK_MT8196 + default COMMON_CLK_MT8196 + help + This driver supports MediaTek MT8196 mcusys clocks. + config COMMON_CLK_MT8196_PEXTPSYS tristate "Clock driver for MediaTek MT8196 pextpsys" depends on COMMON_CLK_MT8196 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 120cf20acdc1..7b284ccc1b48 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -165,6 +165,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o clk-mt8196-peri_ao.o obj-$(CONFIG_COMMON_CLK_MT8196_ADSP) += clk-mt8196-adsp.o obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o +obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o diff --git a/drivers/clk/mediatek/clk-mt8196-mcu.c b/drivers/clk/mediatek/clk-mt8196-mcu.c new file mode 100644 index 000000000000..a08d1597cc88 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8196-mcu.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Guangjie Song + * Copyright (c) 2025 Collabora Ltd. + * Laura Nao + */ +#include +#include +#include +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-pll.h" + +#define ARMPLL_LL_CON0 0x008 +#define ARMPLL_LL_CON1 0x00c +#define ARMPLL_LL_CON2 0x010 +#define ARMPLL_LL_CON3 0x014 +#define ARMPLL_BL_CON0 0x008 +#define ARMPLL_BL_CON1 0x00c +#define ARMPLL_BL_CON2 0x010 +#define ARMPLL_BL_CON3 0x014 +#define ARMPLL_B_CON0 0x008 +#define ARMPLL_B_CON1 0x00c +#define ARMPLL_B_CON2 0x010 +#define ARMPLL_B_CON3 0x014 +#define CCIPLL_CON0 0x008 +#define CCIPLL_CON1 0x00c +#define CCIPLL_CON2 0x010 +#define CCIPLL_CON3 0x014 +#define PTPPLL_CON0 0x008 +#define PTPPLL_CON1 0x00c +#define PTPPLL_CON2 0x010 +#define PTPPLL_CON3 0x014 + +#define MT8196_PLL_FMAX (3800UL * MHZ) +#define MT8196_PLL_FMIN (1500UL * MHZ) +#define MT8196_INTEGER_BITS 8 + +#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \ + _flags, _rst_bar_mask, \ + _pd_reg, _pd_shift, _tuner_reg, \ + _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, _pcwbits) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .en_reg = _en_reg, \ + .en_mask = _en_mask, \ + .pll_en_bit = _pll_en_bit, \ + .flags = _flags, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8196_PLL_FMAX, \ + .fmin = MT8196_PLL_FMIN, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, \ + .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcwbits = _pcwbits, \ + .pcwibits = MT8196_INTEGER_BITS, \ + } + +static const struct mtk_pll_data cpu_bl_plls[] = { + PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0, + 0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22), +}; + +static const struct mtk_pll_data cpu_b_plls[] = { + PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0, + PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22), +}; + +static const struct mtk_pll_data cpu_ll_plls[] = { + PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0, + 0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22), +}; + +static const struct mtk_pll_data cci_plls[] = { + PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO, + BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22), +}; + +static const struct mtk_pll_data ptp_plls[] = { + PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO, + BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22), +}; + +static const struct of_device_id of_match_clk_mt8196_mcu[] = { + { .compatible = "mediatek,mt8196-armpll-bl-pll-ctrl", + .data = &cpu_bl_plls }, + { .compatible = "mediatek,mt8196-armpll-b-pll-ctrl", + .data = &cpu_b_plls }, + { .compatible = "mediatek,mt8196-armpll-ll-pll-ctrl", + .data = &cpu_ll_plls }, + { .compatible = "mediatek,mt8196-ccipll-pll-ctrl", .data = &cci_plls }, + { .compatible = "mediatek,mt8196-ptppll-pll-ctrl", .data = &ptp_plls }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mcu); + +static int clk_mt8196_mcu_probe(struct platform_device *pdev) +{ + const struct mtk_pll_data *plls; + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + const int num_plls = 1; + int r; + + plls = of_device_get_match_data(&pdev->dev); + if (!plls) + return -EINVAL; + + clk_data = mtk_alloc_clk_data(num_plls); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_plls(node, plls, num_plls, clk_data); + if (r) + goto free_clk_data; + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_plls; + + platform_set_drvdata(pdev, clk_data); + + return r; + +unregister_plls: + mtk_clk_unregister_plls(plls, num_plls, clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + + return r; +} + +static void clk_mt8196_mcu_remove(struct platform_device *pdev) +{ + const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev); + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + struct device_node *node = pdev->dev.of_node; + + of_clk_del_provider(node); + mtk_clk_unregister_plls(plls, 1, clk_data); + mtk_free_clk_data(clk_data); +} + +static struct platform_driver clk_mt8196_mcu_drv = { + .probe = clk_mt8196_mcu_probe, + .remove = clk_mt8196_mcu_remove, + .driver = { + .name = "clk-mt8196-mcu", + .of_match_table = of_match_clk_mt8196_mcu, + }, +}; +module_platform_driver(clk_mt8196_mcu_drv); + +MODULE_DESCRIPTION("MediaTek MT8196 mcusys clocks driver"); +MODULE_LICENSE("GPL"); -- 2.39.5