Re: [PATCH 30/30] clk: mediatek: mt8196: Add UFS and PEXTP0/1 reset controllers

AngeloGioacchino Del Regno
2025-06-23T16:02:44Z

Il 23/06/25 14:14, Krzysztof Kozlowski ha scritto:
> On 23/06/2025 12:29, Laura Nao wrote:
>> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>
>> Add definitions to register the reset controllers found in the
>> UFS and PEXTP clock controllers.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> Signed-off-by: Laura Nao <laura.nao@collabora.com>
>> ---
>> drivers/clk/mediatek/clk-mt8196-pextp.c | 36 ++++++++++++++++++++++++
>> drivers/clk/mediatek/clk-mt8196-ufs_ao.c | 25 ++++++++++++++++
>> 2 files changed, 61 insertions(+)
>
> You just added these files. Don't add incomplete driver just to fix it
> later. Add complete driver.
>
> Patch should be squashed.

Laura, feel free to squash the patches.

Cheers,
Angelo

>
> Best regards,
> Krzysztof