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From: kernel test robot <lkp@intel.com>
To: Laura Nao <laura.nao@collabora.com>,
	mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
	angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de,
	richardcochran@gmail.com
Cc: oe-kbuild-all@lists.linux.dev, guangjie.song@mediatek.com,
	wenst@chromium.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
	kernel@collabora.com, Laura Nao <laura.nao@collabora.com>
Subject: Re: [PATCH v2 22/29] clk: mediatek: Add MT8196 mfg clock support
Date: Mon, 30 Jun 2025 04:56:37 +0800	[thread overview]
Message-ID: <202506300416.dbAiyBcI-lkp@intel.com> (raw)
In-Reply-To: <20250624143220.244549-23-laura.nao@collabora.com>

Hi Laura,

kernel test robot noticed the following build warnings:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on linus/master v6.16-rc3 next-20250627]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Laura-Nao/clk-mediatek-clk-pll-Add-set-clr-regs-for-shared-PLL-enable-control/20250624-225217
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link:    https://lore.kernel.org/r/20250624143220.244549-23-laura.nao%40collabora.com
patch subject: [PATCH v2 22/29] clk: mediatek: Add MT8196 mfg clock support
config: arm64-randconfig-r053-20250629 (https://download.01.org/0day-ci/archive/20250630/202506300416.dbAiyBcI-lkp@intel.com/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project e04c938cc08a90ae60440ce22d072ebc69d67ee8)
rustc: rustc 1.78.0 (9b00956e5 2024-04-29)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202506300416.dbAiyBcI-lkp@intel.com/

cocci warnings: (new ones prefixed by >>)
>> drivers/clk/mediatek/clk-mt8196-mfg.c:143:3-8: No need to set .owner here. The core will do it.

vim +143 drivers/clk/mediatek/clk-mt8196-mfg.c

   137	
   138	static struct platform_driver clk_mt8196_mfg_drv = {
   139		.probe = clk_mt8196_mfg_probe,
   140		.remove = clk_mt8196_mfg_remove,
   141		.driver = {
   142			.name = "clk-mt8196-mfg",
 > 143			.owner = THIS_MODULE,
   144			.of_match_table = of_match_clk_mt8196_mfg,
   145		},
   146	};
   147	module_platform_driver(clk_mt8196_mfg_drv);
   148	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


  reply	other threads:[~2025-06-29 21:00 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-24 14:31 [PATCH v2 00/29] Add support for MT8196 clock controllers Laura Nao
2025-06-24 14:31 ` [PATCH v2 01/29] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-06-24 14:31 ` [PATCH v2 02/29] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-06-24 14:31 ` [PATCH v2 03/29] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-06-24 14:31 ` [PATCH v2 04/29] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-06-24 14:31 ` [PATCH v2 05/29] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-06-24 14:31 ` [PATCH v2 06/29] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-06-24 14:31 ` [PATCH v2 07/29] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-06-24 14:31 ` [PATCH v2 08/29] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-06-24 14:32 ` [PATCH v2 09/29] dt-bindings: clock: mediatek: Describe MT8196 peripheral clock controllers Laura Nao
2025-06-24 16:02   ` Krzysztof Kozlowski
2025-06-25  8:20     ` AngeloGioacchino Del Regno
2025-06-25  8:57       ` Krzysztof Kozlowski
2025-06-25  9:45         ` AngeloGioacchino Del Regno
2025-06-25 11:05           ` Krzysztof Kozlowski
2025-06-25 12:42             ` AngeloGioacchino Del Regno
2025-06-27  8:37               ` Krzysztof Kozlowski
2025-06-30  9:21                 ` AngeloGioacchino Del Regno
2025-06-25 11:06           ` Krzysztof Kozlowski
2025-06-25 12:48             ` AngeloGioacchino Del Regno
2025-06-27  8:44               ` Krzysztof Kozlowski
2025-06-24 14:32 ` [PATCH v2 10/29] dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding Laura Nao
2025-06-24 16:03   ` Krzysztof Kozlowski
2025-06-24 16:04     ` Krzysztof Kozlowski
2025-06-25  8:48     ` Laura Nao
2025-06-24 14:32 ` [PATCH v2 11/29] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-06-24 14:32 ` [PATCH v2 12/29] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-07-15  4:53   ` Chen-Yu Tsai
2025-07-15  5:26   ` Chen-Yu Tsai
2025-06-24 14:32 ` [PATCH v2 13/29] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 14/29] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-07-15  7:28   ` Chen-Yu Tsai
2025-07-18  8:31     ` Chen-Yu Tsai
2025-07-22 10:52       ` Laura Nao
2025-06-24 14:32 ` [PATCH v2 15/29] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-06-24 14:32 ` [PATCH v2 16/29] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-06-24 14:32 ` [PATCH v2 17/29] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-06-24 14:32 ` [PATCH v2 18/29] clk: mediatek: Add MT8196 adsp " Laura Nao
2025-07-15  4:36   ` Chen-Yu Tsai
2025-06-24 14:32 ` [PATCH v2 19/29] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-06-24 14:32 ` [PATCH v2 20/29] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-06-24 14:32 ` [PATCH v2 21/29] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-06-24 14:32 ` [PATCH v2 22/29] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-06-29 20:56   ` kernel test robot [this message]
2025-06-24 14:32 ` [PATCH v2 23/29] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 24/29] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 25/29] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-06-24 14:32 ` [PATCH v2 26/29] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 27/29] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 28/29] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-06-24 14:32 ` [PATCH v2 29/29] clk: mediatek: Add MT8196 vencsys " Laura Nao
2025-06-24 15:49 ` [PATCH v2 00/29] Add support for MT8196 clock controllers Nícolas F. R. A. Prado

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