From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9555CAC5A7 for ; Tue, 23 Sep 2025 11:40:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=MyTZIankaLF5a06YDy1KIdFXkQpVaw5MiopvoWPWCGU=; b=Nmi0AUArfGWZj0QHukh2ZBvcgv i6Yy0u59D5cO/ox9dfhmbHwsC3PAjgipbQpyJ/6N8MvQ+0c7GIOOTwpRrUI8dzrQgRFnGEZSDCvvp dLTR6sIc9lHvGe7Prl2kjD5eqH/Q+zCnwB5TSNWYps3APFEbQfC7kU4HT5bJDsdUvjesr2EGDqzWf Z6zFY7ryV4vUeOXjewwihh1dHMQK1f5aaiICLnhALqcWdx+LYP+/SfSo47857IVYPnJhgm30t8Y9+ AxHD/a4cNn09mQcO9wIPWHm+858HEGIzEZjrGxqBrU3NUB2pBwgbn1AwimJd2Xfk+0L1i9wzwCHx0 g86sPkjA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v11O0-0000000DCux-3sWR; Tue, 23 Sep 2025 11:40:44 +0000 Received: from sender4-pp-f112.zoho.com ([136.143.188.112]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v11Ny-0000000DCtm-0y43; Tue, 23 Sep 2025 11:40:43 +0000 ARC-Seal: i=1; a=rsa-sha256; t=1758627628; cv=none; d=zohomail.com; s=zohoarc; b=aRtHitE2Lkq/EfF7wEgpSkAf4X5g04EoWFoekmCCwfrxSgVS+UlgVn0g1QNWM+9armULjiJ2E4WhY6ZNaa9FAVXZR7GCkma9KI0FskwdCblrEopzTL2ShHFHmHv1JkptrDLvByOWI0QlxTW5LXVPLlTy00t4ljMhKN+pN24L6as= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758627628; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=MyTZIankaLF5a06YDy1KIdFXkQpVaw5MiopvoWPWCGU=; b=l+M0HKmpcm7TrTk/c5IUoCs+Gjp8Lo+yBDgXKd0ycghlaOMFofeqDXAlhYLra/EnsiuVFe+YSR1Co7dx8Cwuq4jQQ0J4Sjiec5CiWpK5LJKOhOa9ZgbhtIk79QiCVyaP9hcqjAk9873qbY2seS9sM1zcSp1/QaVCauys28aF+Gs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758627628; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=MyTZIankaLF5a06YDy1KIdFXkQpVaw5MiopvoWPWCGU=; b=OBzEPVHH2FAsETV3tnpdV0TZAk5Qqtk8t9i2/XGEAyEdkzoWaauD9iEI+lbafwRR W9BFMes05sXUHoCGxHPmdN+bY1Vpf42wPRCEsxkiQc5nnVwCjbZqfoP6nKEDYqyVcc3 s4wC/dRg+UeuhOafo1dsaF5IQ302PLbWOR3eNmhQ= Received: by mx.zohomail.com with SMTPS id 1758627625982493.68395226566156; Tue, 23 Sep 2025 04:40:25 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 23 Sep 2025 13:39:54 +0200 Subject: [PATCH v4 1/8] dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250923-mt8196-gpufreq-v4-1-6cd63ade73d6@collabora.com> References: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250923_044042_294445_15A94A63 X-CRM114-Status: GOOD ( 11.60 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to control the power and frequency of the GPU. This is modelled as a power domain and clock provider. It lets us omit the OPP tables from the device tree, as those can now be enumerated at runtime from the MCU. Add the necessary schema logic to handle what this SoC expects in terms of clocks and power-domains. Signed-off-by: Nicolas Frattaroli --- .../bindings/gpu/arm,mali-valhall-csf.yaml | 40 ++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index 7ad5a3ffc5f5c753322eda9e74cc65de89d11c73..860691ce985e560536b6c515b82441ba6d367c46 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -45,7 +45,9 @@ properties: minItems: 1 items: - const: core - - const: coregroup + - enum: + - coregroup + - stacks - const: stacks mali-supply: true @@ -92,7 +94,6 @@ required: - interrupts - interrupt-names - clocks - - mali-supply additionalProperties: false @@ -109,6 +110,29 @@ allOf: power-domains: maxItems: 1 power-domain-names: false + required: + - mali-supply + - if: + properties: + compatible: + contains: + const: mediatek,mt8196-mali + then: + properties: + mali-supply: false + sram-supply: false + operating-points-v2: false + power-domains: + maxItems: 1 + power-domain-names: false + clocks: + maxItems: 2 + clock-names: + items: + - const: core + - const: stacks + required: + - power-domains examples: - | @@ -144,5 +168,17 @@ examples: }; }; }; + - | + gpu@48000000 { + compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf"; + reg = <0x48000000 0x480000>; + clocks = <&gpufreq 0>, <&gpufreq 1>; + clock-names = "core", "stacks"; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + power-domains = <&gpufreq>; + }; ... -- 2.51.0