From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E1A8CAC5B0 for ; Tue, 23 Sep 2025 11:40:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=949P4c7oqZxzyo32GRpJ63no7ggIJKiAuXyyVIYptoo=; b=lyrhz5GBv2syl6bWPBNnvj6Xdy figtMIb+cLEX46SGN7xwWlgdT7Gspcg53LFG9TlWnikz4cbM82aC7RPVFIS9/TXQvUy92+dyuaYhL xCQweELlDaSuczZQlRu5kDKD8ZKXGWByLWljKh7FPzMmtKedEj3Zae57PfCa51+aH71AQwv+LKrlS E9/RjGSDxK+3X3DAsg814XZhei0UI5zWQSJY0/Be9EmqtrYGjsl7OeO8VAQp8KFXD/pGkhm2mOdQK J521hsbuKnPhjT4mkIW2SKvhxtc7OWAHRxPphMUeDGgNnwEZKyuJ2wx1JqLtr2w+PaP2shBT6tMPJ Y2hBU03w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v11O5-0000000DCyk-199u; Tue, 23 Sep 2025 11:40:49 +0000 Received: from sender4-pp-f112.zoho.com ([136.143.188.112]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v11O2-0000000DCwJ-3IR9; Tue, 23 Sep 2025 11:40:48 +0000 ARC-Seal: i=1; a=rsa-sha256; t=1758627634; cv=none; d=zohomail.com; s=zohoarc; b=QC5kBBs7HMf1H3HIKcnYEmgc/l9eNYPZF+SIMhlPf2GBrD6VYRp/AWir0wyTmUNQPwozZq4zn9qn3rxz22QxWoJ1SzGusI4KMjHBQCInK7PPSFZzwMkk6TcVBxQpFoPyJ4RMCicnuoNJwNLHvPpl2VQsJ0tqmmKe7saQ2LCL6vA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758627634; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=949P4c7oqZxzyo32GRpJ63no7ggIJKiAuXyyVIYptoo=; b=QNMa6hnv9FjFyUbnv3zoL0P18DDSB4PBnBeKniCv4Zn67jbSjnkH8zNZdnW5wlKbFebuIvsIrvCpRyiCUpZxLaCb4cmJKzcpCkcaEIEJxvHsvz2S+HLPnsQfXIpY0+42ijYVZGL+yze0joSHyddUj7Gi4EJZhg6Sq7Kl1tSH0Nc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758627634; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=949P4c7oqZxzyo32GRpJ63no7ggIJKiAuXyyVIYptoo=; b=T3FdaC/KTIftSH470aR/Ul2aZLxtVSbyowKqlyeWUei8rzdr/vNAVmtrijsvYiX0 RLGrX/xr7wOKh4jxeEVlLJu2VPbscCew+M9216HP89Dava1o4kWME24fh5sPU4lmmjq /10+uH05ldee9uBdsnlSAt468tPPkVjsTZ/DzX4E= Received: by mx.zohomail.com with SMTPS id 17586276323594.250542151723835; Tue, 23 Sep 2025 04:40:32 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 23 Sep 2025 13:39:55 +0200 Subject: [PATCH v4 2/8] dt-bindings: power: Add MT8196 GPU frequency control binding MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250923-mt8196-gpufreq-v4-2-6cd63ade73d6@collabora.com> References: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250923_044046_904762_8689BEC9 X-CRM114-Status: GOOD ( 13.99 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On the MT8196 and MT6991 SoCs, the GPU power and frequency is controlled by some integration logic, referred to as "MFlexGraphics" by MediaTek, which comes in the form of an embedded controller running special-purpose firmware. This controller takes care of the regulators and PLL clock frequencies to squeeze the maximum amount of power out of the silicon. Add a binding which models it as a power domain. Signed-off-by: Nicolas Frattaroli --- .../bindings/power/mediatek,mt8196-gpufreq.yaml | 117 +++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml new file mode 100644 index 0000000000000000000000000000000000000000..03721244a737ce0914a89cc0aedd88fa3b6b2038 --- /dev/null +++ b/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics Power and Frequency Controller + +maintainers: + - Nicolas Frattaroli + +description: | + A special-purpose embedded MCU to control power and frequency of GPU devices + using MediaTek Flexible Graphics integration hardware. + +properties: + $nodename: + pattern: '^power-controller@[a-f0-9]+$' + + compatible: + enum: + - mediatek,mt8196-gpufreq + + reg: + items: + - description: GPR memory area + - description: RPC memory area + - description: SoC variant ID register + + reg-names: + items: + - const: gpr + - const: rpc + - const: hw-revision + + clocks: + items: + - description: main clock of the embedded controller (EB) + - description: core PLL + - description: stack 0 PLL + - description: stack 1 PLL + + clock-names: + items: + - const: eb + - const: core + - const: stack0 + - const: stack1 + + mboxes: + items: + - description: FastDVFS events + - description: frequency control + - description: sleep control + - description: timer control + - description: frequency hopping control + - description: hardware voter control + - description: FastDVFS control + + mbox-names: + items: + - const: fast-dvfs-event + - const: gpufreq + - const: sleep + - const: timer + - const: fhctl + - const: ccf + - const: fast-dvfs + + shmem: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the shared memory region of the GPUEB MCU + + "#clock-cells": + const: 1 + + "#power-domain-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mboxes + - mbox-names + - shmem + - "#clock-cells" + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + #include + + power-controller@4b09fd00 { + compatible = "mediatek,mt8196-gpufreq"; + reg = <0x4b09fd00 0x80>, + <0x4b800000 0x1000>, + <0x4b860128 0x4>; + reg-names = "gpr", "rpc", "hw-revision"; + clocks = <&topckgen CLK_TOP_MFG_EB>, + <&mfgpll CLK_MFG_AO_MFGPLL>, + <&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>, + <&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>; + clock-names = "eb", "core", "stack0", "stack1"; + mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>, + <&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>, + <&gpueb_mbox 7>; + mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl", + "ccf", "fast-dvfs"; + shmem = <&gpufreq_shmem>; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; -- 2.51.0