From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 495F5CCFA03 for ; Thu, 6 Nov 2025 12:44:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BiI8khDgVdpkkWYW6gy1TP78djT0ma3zFSfJBcQBv78=; b=JD0TZzNYSFv5ByjwBP/n8aj/Nf J0t4RQqEOP7QyvONsvVOv2njII1ATZu+LHyssD+yB/aBHHeVPDULmHCiJkV8q9EPsC2AdKw5/3x5d 4dyO8fcHnYRtYb1LJr/QPiNxLzhpeHpXBSH60amkDyiNAKtYlGux/FkbzPQVvPr3Px1uHqP1I4YfS hMYX/Sq2jxHpgRoSbe6s5sI4iHaQrIJpWJ1UuFmZ9DqGxSmZcmFtoFFLcOIgiXARL13PE7r3OLfgk VCrs1jO4wKGtUEFvFPumIvUAoYof+/D/ahFutPmZ2waNUEsu/3d+vcdEL/qNkFMTA1iNxyuwkj03z Oxcs0ncQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vGzLo-0000000FUV4-1qbr; Thu, 06 Nov 2025 12:44:28 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vGzLE-0000000FTQb-2RXd; Thu, 06 Nov 2025 12:43:58 +0000 X-UUID: 3a034a6cbb0e11f0a52f393f94899d25-20251106 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BiI8khDgVdpkkWYW6gy1TP78djT0ma3zFSfJBcQBv78=; b=hEHLWNB/UBlbI7CC/kbttDLfqRySwvucL2MX3BRgy3GlJ0ml1ZYFsfWWFOCIuCO6WeDumq0OGzafwK1iMklcG54IXjg13BjvIY9u+C5fNczZhFxH//xxVVmD+7TW2JaEb0i5q/BixWlfhEZ4jPCPlJEvP0M5hwXHHe1O/RkdyhE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:ddcd7e25-7204-41da-a3e9-1d6ca116e4fd,IP:0,UR L:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-50 X-CID-META: VersionHash:a9d874c,CLOUDID:dcd934e0-3890-4bb9-a90e-2a6a4ecf6c66,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:2,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 3a034a6cbb0e11f0a52f393f94899d25-20251106 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1827505197; Thu, 06 Nov 2025 05:43:42 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Thu, 6 Nov 2025 20:43:39 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Thu, 6 Nov 2025 20:43:39 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v3 15/21] clk: mediatek: Add MT8189 mfg clock support Date: Thu, 6 Nov 2025 20:42:00 +0800 Message-ID: <20251106124330.1145600-16-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> References: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251106_044352_688259_76BC380F X-CRM114-Status: GOOD ( 19.37 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Irving-CH Lin Add support for the MT8189 mfg clock controller, which provides clock gate control for the GPU. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 11 ++++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-mfg.c | 56 +++++++++++++++++++++++++++ 3 files changed, 68 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-mfg.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index ef962f5816a8..316d010b503a 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -906,6 +906,17 @@ config COMMON_CLK_MT8189_MDPSYS chipset, ensuring that the display system operates efficiently and effectively. +config COMMON_CLK_MT8189_MFG + tristate "Clock driver for MediaTek MT8189 mfg" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this option to support the manufacturing clocks for the MediaTek + MT8189 chipset. This driver provides the necessary clock framework + integration for manufacturing tests and operations that are specific to + the MT8189 chipset. Enabling this will allow the manufacturing mode of + the chipset to function correctly with the appropriate clock settings. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 9b23e4c5e019..07f11760cf68 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -132,6 +132,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o obj-$(CONFIG_COMMON_CLK_MT8189_IMG) += clk-mt8189-img.o obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) += clk-mt8189-mdpsys.o +obj-$(CONFIG_COMMON_CLK_MT8189_MFG) += clk-mt8189-mfg.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-mfg.c b/drivers/clk/mediatek/clk-mt8189-mfg.c new file mode 100644 index 000000000000..d4c20118247f --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-mfg.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs mfg_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_MFG(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &mfg_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + .flags = CLK_OPS_PARENT_ENABLE | CLK_IGNORE_UNUSED, \ + } + +static const struct mtk_gate mfg_clks[] = { + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel_mfgpll", 0), +}; + +static const struct mtk_clk_desc mfg_mcd = { + .clks = mfg_clks, + .num_clks = ARRAY_SIZE(mfg_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_mfg[] = { + { .compatible = "mediatek,mt8189-mfgcfg", .data = &mfg_mcd }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8189_mfg_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8189-mfg", + .of_match_table = of_match_clk_mt8189_mfg, + }, +}; + +module_platform_driver(clk_mt8189_mfg_drv); +MODULE_LICENSE("GPL"); -- 2.45.2