From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE8FCCCFA1D for ; Thu, 6 Nov 2025 12:44:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SlAZG/Cb96N+FkjWIPTfoSRw7durJpX66cHIrZcfaKo=; b=W10KeVr/klbn4WcloYAPLiEgjc 0suh6QAZdfGx6U2aL3yP92UT7pbAxFClqEmLiOTE3lelWGrdjcncRcHkP89BAUzBJLwWsg20wvpyn Kcp+QkCmIxics+A4Ut3aNVX30QbcP3IR9+vUuJMCgwd46r7MUowFUbZpi0oPjw9hM9yGeSTs+EJpQ XXvx9MmFD5Bb/+NJkTQ5GPwTB+0FXMedyYTGG/VFucK/iln3iu4Kb6GP1K2T4pNWrw8eQCIKeOaQj m04Pub+GDnfh5vWxwCce3mckhYNEeY6Sr7xdRbTcmqFSJdxtXLvqniO566phLEWy8pazIcgC3sR+M InrwzVrQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vGzLi-0000000FUIL-1BcN; Thu, 06 Nov 2025 12:44:22 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vGzLE-0000000FTQX-1E1g; Thu, 06 Nov 2025 12:43:56 +0000 X-UUID: 3a669bdabb0e11f0a52f393f94899d25-20251106 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=SlAZG/Cb96N+FkjWIPTfoSRw7durJpX66cHIrZcfaKo=; b=BPfW99sZDZkF65IrzWpg5gx8Y33OX+7lCX1mJu8qdQSadxdHnWvPsn5DRgkSPY3fNCQJkuQ+Sh9CZxFdlzIM5ZVS5FAgvubnEFCCV69QcyUklxovSP5Aq3RXowIfWoiRmRvL76eAe1YksSlNhsNFI5NBzrckai4/l9hUrVb+NvE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:035adb9b-dc82-418e-a68a-d090e6906ccb,IP:0,UR L:0,TC:0,Content:-5,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:a9d874c,CLOUDID:f313fc7c-f9d7-466d-a1f7-15b5fcad2ce6,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:2,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 3a669bdabb0e11f0a52f393f94899d25-20251106 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1760124213; Thu, 06 Nov 2025 05:43:43 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Thu, 6 Nov 2025 20:43:39 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Thu, 6 Nov 2025 20:43:39 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v3 17/21] clk: mediatek: Add MT8189 scp clock support Date: Thu, 6 Nov 2025 20:42:02 +0800 Message-ID: <20251106124330.1145600-18-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> References: <20251106124330.1145600-1-irving-ch.lin@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251106_044352_430041_1E806C5E X-CRM114-Status: GOOD ( 18.57 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Irving-CH Lin Add support for the MT8189 scp clock controller, which provides clock gate control for System Control Processor. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 10 ++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-scp.c | 84 +++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-scp.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 8b1f358457d8..2cc1a28436f1 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -929,6 +929,16 @@ config COMMON_CLK_MT8189_MMSYS ensure that these components receive the correct clock frequencies for proper operation. +config COMMON_CLK_MT8189_SCP + tristate "Clock driver for MediaTek MT8189 scp" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock framework for the System Control + Processor (SCP) in the MediaTek MT8189 SoC. This includes clock + management for SCP-related features, ensuring proper clock + distribution and gating for power efficiency and functionality. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 21a9e6264b84..819c67395e1b 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -134,6 +134,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_IMG) += clk-mt8189-img.o obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) += clk-mt8189-mdpsys.o obj-$(CONFIG_COMMON_CLK_MT8189_MFG) += clk-mt8189-mfg.o obj-$(CONFIG_COMMON_CLK_MT8189_MMSYS) += clk-mt8189-dispsys.o +obj-$(CONFIG_COMMON_CLK_MT8189_SCP) += clk-mt8189-scp.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-scp.c b/drivers/clk/mediatek/clk-mt8189-scp.c new file mode 100644 index 000000000000..def4a0e388b9 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-scp.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs scp_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x4, +}; + +#define GATE_SCP(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &scp_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr_inv, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + } + +static const struct mtk_gate scp_clks[] = { + GATE_SCP(CLK_SCP_SET_SPI0, "scp_set_spi0", "clk26m", 0), + GATE_SCP(CLK_SCP_SET_SPI1, "scp_set_spi1", "clk26m", 1), +}; + +static const struct mtk_clk_desc scp_mcd = { + .clks = scp_clks, + .num_clks = ARRAY_SIZE(scp_clks), +}; + +static const struct mtk_gate_regs scp_iic_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x4, + .sta_ofs = 0x0, +}; + +#define GATE_SCP_IIC(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &scp_iic_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr_inv, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + } + +static const struct mtk_gate scp_iic_clks[] = { + GATE_SCP_IIC(CLK_SCP_IIC_I2C0_W1S, "scp_iic_i2c0_w1s", "vlp_scp_iic_sel", 0), + GATE_SCP_IIC(CLK_SCP_IIC_I2C1_W1S, "scp_iic_i2c1_w1s", "vlp_scp_iic_sel", 1), +}; + +static const struct mtk_clk_desc scp_iic_mcd = { + .clks = scp_iic_clks, + .num_clks = ARRAY_SIZE(scp_iic_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_scp[] = { + { .compatible = "mediatek,mt8189-scp-clk", .data = &scp_mcd }, + { .compatible = "mediatek,mt8189-scp-i2c-clk", .data = &scp_iic_mcd }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8189_scp_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8189-scp", + .of_match_table = of_match_clk_mt8189_scp, + }, +}; + +module_platform_driver(clk_mt8189_scp_drv); +MODULE_LICENSE("GPL"); -- 2.45.2