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From: irving.ch.lin <irving-ch.lin@mediatek.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Richard Cochran <richardcochran@gmail.com>
Cc: Qiqi Wang <qiqi.wang@mediatek.com>, <linux-clk@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>, <linux-pm@vger.kernel.org>,
	<netdev@vger.kernel.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	<sirius.wang@mediatek.com>, <vince-wl.liu@mediatek.com>,
	<jh.hsu@mediatek.com>, <irving-ch.lin@mediatek.com>
Subject: [PATCH v3 20/21] pmdomain: mediatek: Add bus protect control flow for MT8189
Date: Thu, 6 Nov 2025 20:42:05 +0800	[thread overview]
Message-ID: <20251106124330.1145600-21-irving-ch.lin@mediatek.com> (raw)
In-Reply-To: <20251106124330.1145600-1-irving-ch.lin@mediatek.com>

From: Irving-CH Lin <irving-ch.lin@mediatek.com>

In MT8189 mminfra power domain, the bus protect policy separates
into two parts, one is set before subsys clocks enabled, and another
need to enable after subsys clocks enable.

Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
---
 drivers/pmdomain/mediatek/mtk-pm-domains.c | 31 ++++++++++++++++++----
 drivers/pmdomain/mediatek/mtk-pm-domains.h |  5 ++++
 2 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
index 164c6b519af3..222846e52daf 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
@@ -250,7 +250,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
 					MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
 }
 
-static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
+static int scpsys_bus_protect_enable(struct scpsys_domain *pd, u8 flags)
 {
 	for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
 		const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
@@ -259,6 +259,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
 		if (!bpd->bus_prot_set_clr_mask)
 			break;
 
+		if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
+		    (flags & BUS_PROT_IGNORE_SUBCLK))
+			continue;
+
 		if (bpd->flags & BUS_PROT_INVERTED)
 			ret = scpsys_bus_protect_clear(pd, bpd);
 		else
@@ -270,7 +274,7 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
 	return 0;
 }
 
-static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
+static int scpsys_bus_protect_disable(struct scpsys_domain *pd, u8 flags)
 {
 	for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
 		const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
@@ -279,6 +283,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
 		if (!bpd->bus_prot_set_clr_mask)
 			continue;
 
+		if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
+		    (flags & BUS_PROT_IGNORE_SUBCLK))
+			continue;
+
 		if (bpd->flags & BUS_PROT_INVERTED)
 			ret = scpsys_bus_protect_set(pd, bpd);
 		else
@@ -632,6 +640,15 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
 	if (ret)
 		goto err_pwr_ack;
 
+	/*
+	 * In MT8189 mminfra power domain, the bus protect policy separates
+	 * into two parts, one is set before subsys clocks enabled, and another
+	 * need to enable after subsys clocks enable.
+	 */
+	ret = scpsys_bus_protect_disable(pd, BUS_PROT_IGNORE_SUBCLK);
+	if (ret < 0)
+		goto err_pwr_ack;
+
 	/*
 	 * In few Mediatek platforms(e.g. MT6779), the bus protect policy is
 	 * stricter, which leads to bus protect release must be prior to bus
@@ -648,7 +665,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
 	if (ret < 0)
 		goto err_disable_subsys_clks;
 
-	ret = scpsys_bus_protect_disable(pd);
+	ret = scpsys_bus_protect_disable(pd, 0);
 	if (ret < 0)
 		goto err_disable_sram;
 
@@ -662,7 +679,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
 	return 0;
 
 err_enable_bus_protect:
-	scpsys_bus_protect_enable(pd);
+	scpsys_bus_protect_enable(pd, 0);
 err_disable_sram:
 	scpsys_sram_disable(pd);
 err_disable_subsys_clks:
@@ -683,7 +700,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
 	bool tmp;
 	int ret;
 
-	ret = scpsys_bus_protect_enable(pd);
+	ret = scpsys_bus_protect_enable(pd, 0);
 	if (ret < 0)
 		return ret;
 
@@ -697,6 +714,10 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
 
 	clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
 
+	ret = scpsys_bus_protect_enable(pd, BUS_PROT_IGNORE_SUBCLK);
+	if (ret < 0)
+		return ret;
+
 	if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ))
 		scpsys_modem_pwrseq_off(pd);
 	else
diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h
index f608e6ec4744..a5dca24cbc2f 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h
@@ -56,6 +56,7 @@ enum scpsys_bus_prot_flags {
 	BUS_PROT_REG_UPDATE = BIT(1),
 	BUS_PROT_IGNORE_CLR_ACK = BIT(2),
 	BUS_PROT_INVERTED = BIT(3),
+	BUS_PROT_IGNORE_SUBCLK = BIT(4),
 };
 
 enum scpsys_bus_prot_block {
@@ -95,6 +96,10 @@ enum scpsys_bus_prot_block {
 		_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta,	\
 			  BUS_PROT_REG_UPDATE)
 
+#define BUS_PROT_WR_IGN_SUBCLK(_hwip, _mask, _set, _clr, _sta)		\
+		_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta,	\
+			  BUS_PROT_IGNORE_CLR_ACK | BUS_PROT_IGNORE_SUBCLK)
+
 #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask)			\
 		BUS_PROT_UPDATE(INFRA, _mask,			\
 				INFRA_TOPAXI_PROTECTEN,		\
-- 
2.45.2



  parent reply	other threads:[~2025-11-06 12:43 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-06 12:41 [PATCH v3 00/21] Add support for MT8189 clock/power controller irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 01/21] dt-bindings: clock: mediatek: Add MT8189 clock definitions irving.ch.lin
2025-11-06 17:19   ` Conor Dooley
2025-12-10 10:01     ` Irving-CH Lin (林建弘)
2025-12-10 16:33       ` Conor Dooley
2025-11-07  7:27   ` Krzysztof Kozlowski
2025-11-27 10:30   ` Louis-Alexis Eyraud
2025-11-06 12:41 ` [PATCH v3 02/21] dt-bindings: power: mediatek: Add MT8189 power domain definitions irving.ch.lin
2025-11-06 13:34   ` Rob Herring (Arm)
2025-11-06 17:17     ` Conor Dooley
2025-11-07  7:26       ` Krzysztof Kozlowski
2025-11-07 16:58         ` Conor Dooley
2025-11-06 12:41 ` [PATCH v3 03/21] clk: mediatek: fix mfg mux issue irving.ch.lin
2025-11-07  9:34   ` AngeloGioacchino Del Regno
2025-11-06 12:41 ` [PATCH v3 04/21] clk: mediatek: Add MT8189 apmixedsys clock support irving.ch.lin
2025-11-27 12:04   ` Louis-Alexis Eyraud
2025-11-06 12:41 ` [PATCH v3 05/21] clk: mediatek: Add MT8189 topckgen " irving.ch.lin
2025-11-27 13:46   ` Louis-Alexis Eyraud
2025-12-10 10:41     ` Irving-CH Lin (林建弘)
2025-11-06 12:41 ` [PATCH v3 06/21] clk: mediatek: Add MT8189 vlpckgen " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 07/21] clk: mediatek: Add MT8189 vlpcfg " irving.ch.lin
2025-11-27 16:03   ` Louis-Alexis Eyraud
2025-11-06 12:41 ` [PATCH v3 08/21] clk: mediatek: Add MT8189 bus " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 09/21] clk: mediatek: Add MT8189 cam " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 10/21] clk: mediatek: Add MT8189 dbgao " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 11/21] clk: mediatek: Add MT8189 dvfsrc " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 12/21] clk: mediatek: Add MT8189 i2c " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 13/21] clk: mediatek: Add MT8189 img " irving.ch.lin
2025-11-06 12:41 ` [PATCH v3 14/21] clk: mediatek: Add MT8189 mdp " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 15/21] clk: mediatek: Add MT8189 mfg " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 16/21] clk: mediatek: Add MT8189 mmsys " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 17/21] clk: mediatek: Add MT8189 scp " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 18/21] clk: mediatek: Add MT8189 ufs " irving.ch.lin
2025-11-06 12:42 ` [PATCH v3 19/21] clk: mediatek: Add MT8189 vcodec " irving.ch.lin
2025-11-06 12:42 ` irving.ch.lin [this message]
2025-11-07 10:36   ` [PATCH v3 20/21] pmdomain: mediatek: Add bus protect control flow for MT8189 AngeloGioacchino Del Regno
2025-12-10 10:30     ` Irving-CH Lin (林建弘)
2025-11-06 12:42 ` [PATCH v3 21/21] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin

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