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Tue, 20 Jan 2026 03:37:49 -0800 (PST) Received: from [127.0.1.1] ([2001:861:3201:3d10:9fa0:1400:5c26:1419]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c5edf264b9csm11462134a12.15.2026.01.20.03.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jan 2026 03:37:48 -0800 (PST) From: Gary Bisson Date: Tue, 20 Jan 2026 12:36:59 +0100 Subject: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> X-B4-Tracking: v=1; b=H4sIANpob2kC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDQyMD3dyS7JTiTF0jy1STZAuTVPMkYwsloOKCotS0zAqwQdGxtbUAlxA E9VgAAAA= X-Change-ID: 20260120-mtkdsi-29e4c84e7b38 To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gary Bisson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768909063; l=2852; i=bisson.gary@gmail.com; s=20251201; h=from:subject:message-id; bh=ETsLcSZWKB9eq3Cr6keAewRWPWzheGP6F9hf6pabzj8=; b=vFf5Qdlbwe4FiGiI83Db84ydmZAaWLQ3TMiZXuLTGwCAwsOUAzY4UJTj0cTS0qPmPPd3VjN5F RL5WhoIxZDkAMo+KcW2ej0+SI1Sze9wVe2bNPa23aYLM49ontoyVwcq X-Developer-Key: i=bisson.gary@gmail.com; a=ed25519; pk=eaOrLwovHUZBMoLbrx+L1ppj+AH+TfgxkVhIEyrhkeE= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260120_033750_623903_E8603A8C X-CRM114-Status: GOOD ( 13.37 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Some bridges, such as the TI SN65DSI83, require the HS clock to be running in order to lock its PLL during its own pre-enable function. Without this change, the bridge gives the following error: sn65dsi83 14-002c: failed to lock PLL, ret=-110 sn65dsi83 14-002c: Unexpected link status 0x01 sn65dsi83 14-002c: reset the pipe Move the necessary functions from enable to pre-enable. Signed-off-by: Gary Bisson --- Tested on Tungsten510 module with sn65dsi83 + tm070jdhg30 panel. Left mtk_dsi_set_mode() as part of the enable function to mimic what is done in the Samsung DSIM driver which is known to be working the TI bridge. --- drivers/gpu/drm/mediatek/mtk_dsi.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 0e2bcd5f67b7..b560245d1be9 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -672,6 +672,21 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) } } +static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) +{ + if (!dsi->lanes_ready) { + dsi->lanes_ready = true; + mtk_dsi_rxtx_control(dsi); + usleep_range(30, 100); + mtk_dsi_reset_dphy(dsi); + mtk_dsi_clk_ulp_mode_leave(dsi); + mtk_dsi_lane0_ulp_mode_leave(dsi); + mtk_dsi_clk_hs_mode(dsi, 0); + usleep_range(1000, 3000); + /* The reaction time after pulling up the mipi signal for dsi_rx */ + } +} + static int mtk_dsi_poweron(struct mtk_dsi *dsi) { struct device *dev = dsi->host.dev; @@ -724,6 +739,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_set_vm_cmd(dsi); mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); + mtk_dsi_lane_ready(dsi); + mtk_dsi_clk_hs_mode(dsi, 1); return 0; err_disable_engine_clk: @@ -769,30 +786,12 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) dsi->lanes_ready = false; } -static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) -{ - if (!dsi->lanes_ready) { - dsi->lanes_ready = true; - mtk_dsi_rxtx_control(dsi); - usleep_range(30, 100); - mtk_dsi_reset_dphy(dsi); - mtk_dsi_clk_ulp_mode_leave(dsi); - mtk_dsi_lane0_ulp_mode_leave(dsi); - mtk_dsi_clk_hs_mode(dsi, 0); - usleep_range(1000, 3000); - /* The reaction time after pulling up the mipi signal for dsi_rx */ - } -} - static void mtk_output_dsi_enable(struct mtk_dsi *dsi) { if (dsi->enabled) return; - mtk_dsi_lane_ready(dsi); mtk_dsi_set_mode(dsi); - mtk_dsi_clk_hs_mode(dsi, 1); - mtk_dsi_start(dsi); dsi->enabled = true; --- base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8 change-id: 20260120-mtkdsi-29e4c84e7b38 Best regards, -- Gary Bisson