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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Caleb James DeLisle <cjd@cjdns.fr>
Cc: linux-mips@vger.kernel.org, naseefkm@gmail.com,
	 mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org,  conor+dt@kernel.org,
	tsbogend@alpha.franken.de, ryder.lee@mediatek.com,
	 jianjun.wang@mediatek.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org,  bhelgaas@google.com,
	vkoul@kernel.org, neil.armstrong@linaro.org,
	 p.zabel@pengutronix.de, matthias.bgg@gmail.com,
	angelogioacchino.delregno@collabora.com,  nbd@nbd.name,
	ansuelsmth@gmail.com, linux-clk@vger.kernel.org,
	 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org,  linux-mediatek@lists.infradead.org,
	linux-phy@lists.infradead.org,
	 linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/8] dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528
Date: Tue, 10 Mar 2026 09:24:08 +0100	[thread overview]
Message-ID: <20260310-scrupulous-fat-ara-eab47c@quoll> (raw)
In-Reply-To: <20260309131818.74467-4-cjd@cjdns.fr>

On Mon, Mar 09, 2026 at 01:18:13PM +0000, Caleb James DeLisle wrote:
> EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY
> which behaves slightly differently because one slot is Gen1/Gen2 while
> the other is Gen1 only.
> 
> Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>

Still, four separate subsystems unnecessarily merged into one patchset.
Split independent parts of your work per subsystem. See also submitting
patches.

> ---
>  .../phy/econet,en751221-pcie-phy.yaml         | 50 +++++++++++++++++++
>  MAINTAINERS                                   |  6 +++
>  2 files changed, 56 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof



  reply	other threads:[~2026-03-10  8:24 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-09 13:18 [PATCH v2 0/8] mips: econet: Add clk/reset and PCIe support Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 1/8] dt-bindings: clock, reset: Add econet EN751221 Caleb James DeLisle
2026-03-10  8:21   ` Krzysztof Kozlowski
2026-03-10  8:37     ` Caleb James DeLisle
2026-03-10  8:51       ` Krzysztof Kozlowski
2026-03-09 13:18 ` [PATCH v2 2/8] clk: airoha: Add econet EN751221 clock/reset support to en7523-scu Caleb James DeLisle
2026-03-11 14:39   ` Brian Masney
2026-03-11 17:12     ` Caleb James DeLisle
2026-03-11 19:44       ` Brian Masney
2026-03-09 13:18 ` [PATCH v2 3/8] dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528 Caleb James DeLisle
2026-03-10  8:24   ` Krzysztof Kozlowski [this message]
2026-03-10 10:37     ` Caleb James DeLisle
2026-03-10 10:40       ` Krzysztof Kozlowski
2026-03-10 10:40         ` Krzysztof Kozlowski
2026-03-10 11:13         ` Caleb James DeLisle
2026-03-10 11:20           ` Krzysztof Kozlowski
2026-03-09 13:18 ` [PATCH v2 4/8] phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 5/8] dt-bindings: PCI: mediatek: Add support for EcoNet EN7528 Caleb James DeLisle
2026-03-10  8:25   ` Krzysztof Kozlowski
2026-03-10  8:49     ` Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 6/8] PCI: mediatek: Add support for EcoNet EN7528 SoC Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 7/8] PCI: Skip bridge window reads when window is not supported Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 8/8] mips: dts: Add PCIe to EcoNet EN751221 Caleb James DeLisle

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