From: <ed.tsai@mediatek.com>
To: <bvanassche@acm.org>, Alim Akhtar <alim.akhtar@samsung.com>,
Avri Altman <avri.altman@wdc.com>,
"James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>,
"Martin K. Petersen" <martin.petersen@oracle.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <wsd_upstream@mediatek.com>,
<peter.wang@mediatek.com>, <alice.chao@mediatek.com>,
<naomi.chu@mediatek.com>, <chun-hung.wu@mediatek.com>,
Ed Tsai <ed.tsai@mediatek.com>, <linux-scsi@vger.kernel.org>
Subject: [PATCH v2 1/2] ufs: core: Add quirks for VCC ramp-up delay
Date: Tue, 10 Mar 2026 08:52:28 +0800 [thread overview]
Message-ID: <20260310005230.4001904-4-ed.tsai@mediatek.com> (raw)
In-Reply-To: <20260310005230.4001904-2-ed.tsai@mediatek.com>
From: Ed Tsai <ed.tsai@mediatek.com>
On some platforms, the VCC regulator has a slow ramp-up time. Add a
delay after enabling VCC to ensure voltage has fully stabilized before
we enable the clocks.
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Ed Tsai <ed.tsai@mediatek.com>
---
drivers/ufs/core/ufshcd.c | 12 ++++++++++++
include/ufs/ufshcd.h | 6 ++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 899e663fea6e..bea72e7c1d32 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -9942,11 +9942,13 @@ static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
#ifdef CONFIG_PM
static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
{
+ bool vcc_on = false;
int ret = 0;
if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
!hba->dev_info.is_lu_power_on_wp) {
ret = ufshcd_setup_vreg(hba, true);
+ vcc_on = true;
} else if (!ufshcd_is_ufs_dev_active(hba)) {
if (!ufshcd_is_link_active(hba)) {
ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
@@ -9957,6 +9959,7 @@ static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
goto vccq_lpm;
}
ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
+ vcc_on = true;
}
goto out;
@@ -9965,6 +9968,15 @@ static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
vcc_disable:
ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
out:
+ /*
+ * On platforms with a slow VCC ramp-up, a delay is needed after
+ * turning on VCC to ensure the voltage is stable before the
+ * reference clock is enabled.
+ */
+ if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on &&
+ hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
+ usleep_range(1000, 1100);
+
return ret;
}
#endif /* CONFIG_PM */
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index 8563b6648976..ee5f1c60174f 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -690,6 +690,12 @@ enum ufshcd_quirks {
* because it causes link startup to become unreliable.
*/
UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE = 1 << 26,
+
+ /*
+ * On some platforms, the VCC regulator has a slow ramp-up time. Add a
+ * delay after enabling VCC to ensure it's stable.
+ */
+ UFSHCD_QUIRK_VCC_ON_DELAY = 1 << 27,
};
enum ufshcd_caps {
--
2.45.2
next prev parent reply other threads:[~2026-03-10 0:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-10 0:52 [PATCH v2 0/2] ufs: add delay for VCC ramp-up stability ed.tsai
2026-03-10 0:52 ` ed.tsai [this message]
2026-03-11 1:43 ` [PATCH v2 1/2] ufs: core: Add quirks for VCC ramp-up delay Martin K. Petersen
2026-03-11 9:23 ` Julian Calaby
2026-03-10 0:52 ` [PATCH v2 2/2] ufs: host: mediatek: Add VCC on delay for stability ed.tsai
2026-03-10 17:43 ` Bart Van Assche
2026-03-16 1:41 ` [PATCH v2 0/2] ufs: add delay for VCC ramp-up stability Martin K. Petersen
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