From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E7C51093172 for ; Fri, 20 Mar 2026 03:21:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=PhHH1eFF51u/zNrMzfxhIKmtLMJpZ4bBYigWRekSPi0=; b=kO+xyOybDd57XyWeq1CCQtsJca +Oft5QN+6TRTVwG/7nxNBB0uqXYbXwxGVBSg79S+khqkxS3htPy2KdN/vHEYUHnNPam11pBXluRpG CAaXgS3EpGjG/VoQDU0ScwUbAuyHEs8qcRKeb+CsDyTJs+Fe8hdD6Zu1Rk693DdaGpUvPaa++PCeh VReOkSYNxT0NEPwH14dStZBxGHqEMNBzw0TUYSYKIZhOR0e1BpXBqPlWeS+b/pDotbDgjPZD3s4Dj 4pKikXEwXevSs27QKqKFYDmS6EqrwTD7DlA4QacPGFVTSwo0ut5GnZCVm6W4jgYVZcqbvnz3aR/kQ ejbAXXHQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1w3QQ5-0000000BzmO-0XGn; Fri, 20 Mar 2026 03:21:05 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1w3QPy-0000000BzkH-3E4w; Fri, 20 Mar 2026 03:21:03 +0000 X-UUID: ccd53efc240b11f1a6de359d7043e138-20260319 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=PhHH1eFF51u/zNrMzfxhIKmtLMJpZ4bBYigWRekSPi0=; b=dT7GIKylHdOx8YTiaA/gc4j1FU8Bq2RwWiK6fXEus/Q1WTzARqwiUYNQqpfnI3P+sbXAUcDBsugtLb7hU/bzs5nHF0JYx6vuNDWtVibhftO+gWIPqqDeWnQu96w/3Sk13bdEUTdLMmOziuksrSPLcGFjB3842MAfwcnw6CLs33w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:582a471e-e3a9-4fdf-885b-1702e510effc,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:e7bac3a,CLOUDID:cf8ee916-aa6b-4b2e-be76-373ef1a42b04,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:97|99|83|106|11|1,File:130,RT:0,Bulk:nil,QS:nil, BEC:-1,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: ccd53efc240b11f1a6de359d7043e138-20260319 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 840934837; Thu, 19 Mar 2026 20:20:52 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 20 Mar 2026 11:20:49 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 20 Mar 2026 11:20:48 +0800 From: Xiangzhi Tang To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Xiangzhi Tang CC: , , , , , , Hailong Fan , Huayu Zong , Xiangzhi Tang Subject: [PATCH v3 1/6] dt-bindings: remoteproc: Add VCP support for mt8196 Date: Fri, 20 Mar 2026 11:18:03 +0800 Message-ID: <20260320032014.13608-2-xiangzhi.tang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260320032014.13608-1-xiangzhi.tang@mediatek.com> References: <20260320032014.13608-1-xiangzhi.tang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260319_202059_105061_37FAF6BB X-CRM114-Status: GOOD ( 14.70 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add the new binding document for MediaTek Video Companion Processor(VCP) on MediaTek mt8196. Signed-off-by: Xiangzhi Tang --- .../remoteproc/mediatek,mt8196-vcp.yaml | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/mediatek,mt8196-vcp.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/mediatek,mt8196-vcp.yaml b/Documentation/devicetree/bindings/remoteproc/mediatek,mt8196-vcp.yaml new file mode 100644 index 000000000000..7ec1ec69537a --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/mediatek,mt8196-vcp.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/mediatek,mt8196-vcp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Video Companion Processor (VCP) + +maintainers: + - Xiangzhi Tang + +description: + The MediaTek VCP enables the SoC control the MediaTek Video Companion Risc-V coprocessor. + +properties: + compatible: + enum: + - mediatek,mt8196-vcp + + reg: + items: + - description: sram base + - description: cfg group IO + - description: cfg core group IO + - description: cfg sec group IO + + reg-names: + items: + - const: sram + - const: cfg + - const: cfg_core + - const: cfg_sec + + interrupts: + maxItems: 1 + + mboxes: + maxItems: 5 + + mbox-names: + maxItems: 5 + + power-domains: + maxItems: 1 + + iommus: + description: + Using MediaTek iommu to apply larb ports for Multimedia Memory + Management Unit and address translation + Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml + maxItems: 1 + + memory-region: + maxItems: 1 + +patternProperties: + "^vcp@[a-f0-9]+$": + type: object + description: + The MediaTek VCP integrated to SoC might be a multi-core version. + The other cores are represented as child nodes of the boot core. + There are some integration differences for the IP like the usage of + address translator for translating SoC bus addresses into address + space for the processor. + + The SRAM are shared by all cores, each VCP core only using a piece + SRAM memory. The power of SRAM should be enabled before booting VCP cores. + The size of SRAM are varied on differnt SoCs. + + The VCP cores has differences on different SoCs to support for + Hart. + + properties: + compatible: + enum: + - mediatek,vcp-core + + reg: + description: The base address and size of SRAM. + maxItems: 1 + + reg-names: + const: sram + + mtk,vcp-core-twohart: + enum: [0, 1] + $ref: /schemas/types.yaml#/definitions/uint32 + + mtk,vcp-sram-offset: + description: + Allocated SRAM memory for each VCP core used. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - compatible + - reg + - reg-names + - mtk,vcp-core-twohart + - mtk,vcp-sram-offset + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - mboxes + - mbox-names + - power-domains + - iommus + - memory-region + +additionalProperties: false + +examples: + - | + #include + #include + #include + + vcp: vcp@31800000 { + compatible = "mediatek,mt8196-vcp"; + reg = <0x31800000 0x60000>, + <0x31a04000 0xa000>, + <0x31bd0000 0x1000>, + <0x31a70020 0x100>, + reg-names = "sram", + "cfg", + "cfg_core", + "cfg_sec"; + + interrupts = ; + + mboxes = <&vcp_mailbox0>, + <&vcp_mailbox1>, + <&vcp_mailbox2>, + <&vcp_mailbox3>, + <&vcp_mailbox4>; + mbox-names = "mbox0", "mbox1", "mbox2", "mbox3", "mbox4"; + + power-domains = <&scpsys MT8196_POWER_DOMAIN_MM_PROC_DORMANT>; + iommus = <&mm_smmu 160>; + memory-region = <&vcp_resv_mem>; + + vcp@0 { + compatible = "mediatek,vcp-core"; + reg = <0x0 0x31000>; + reg-names = "sram"; + mtk,vcp-core-twohart = <1>; + mtk,vcp-sram-offset = <0x0>; + }; + + vcp@31000 { + compatible = "mediatek,vcp-core"; + reg = <0x31000 0x60000>; + reg-names = "sram"; + mtk,vcp-core-twohart = <0>; + mtk,vcp-sram-offset = <0x31000>; + }; + }; -- 2.46.0