Re: [PATCH] PCI: mediatek-gen3: Fix 64-bit type truncation in mtk_pcie_set_trans_table()

[kernel test robot <lkp@intel.com>]

Hi Sreeraj,

kernel test robot noticed the following build errors:

[auto build test ERROR on pci/next]
[also build test ERROR on pci/for-linus linus/master v7.2-rc6 next-20260803]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Sreeraj-S-Kurup/PCI-mediatek-gen3-Fix-64-bit-type-truncation-in-mtk_pcie_set_trans_table/20260728-183948
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20260728101413.4575-1-sreekuttan2156239%40gmail.com
patch subject: [PATCH] PCI: mediatek-gen3: Fix 64-bit type truncation in mtk_pcie_set_trans_table()
config: csky-allmodconfig (https://download.01.org/0day-ci/archive/20260805/202608050123.GZC7hug7-lkp@intel.com/config)
compiler: csky-linux-gcc (GCC) 16.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260805/202608050123.GZC7hug7-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202608050123.GZC7hug7-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from include/linux/bits.h:5,
                    from include/linux/bitops.h:6,
                    from include/linux/kernel.h:23,
                    from include/linux/clk.h:13,
                    from drivers/pci/controller/pcie-mediatek-gen3.c:10:
   drivers/pci/controller/pcie-mediatek-gen3.c: In function 'mtk_pcie_set_trans_table':
>> drivers/pci/controller/pcie-mediatek-gen3.c:340:46: error: implicit declaration of function 'ffs64'; did you mean 'fls64'? [-Wimplicit-function-declaration]
     340 |                         addr_align = BIT_ULL(ffs64(cpu_addr) - 1);
         |                                              ^~~~~
   include/vdso/bits.h:8:45: note: in definition of macro 'BIT_ULL'
       8 | #define BIT_ULL(nr)             (ULL(1) << (nr))
         |                                             ^~


vim +340 drivers/pci/controller/pcie-mediatek-gen3.c

   321	
   322	static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie,
   323					    resource_size_t cpu_addr,
   324					    resource_size_t pci_addr,
   325					    resource_size_t size,
   326					    unsigned long type, int *num)
   327	{
   328		resource_size_t remaining = size;
   329		resource_size_t table_size;
   330		resource_size_t addr_align;
   331		const char *range_type;
   332		void __iomem *table;
   333		u32 val;
   334	
   335		while (remaining && (*num < PCIE_MAX_TRANS_TABLES)) {
   336			/* Table size needs to be a power of 2 */
   337			table_size = BIT_ULL(fls64(remaining) - 1);
   338	
   339			if (cpu_addr > 0) {
 > 340				addr_align = BIT_ULL(ffs64(cpu_addr) - 1);
   341				table_size = min(table_size, addr_align);
   342			}
   343	
   344			/* Minimum size of translate table is 4KiB */
   345			if (table_size < 0x1000) {
   346				dev_err(pcie->dev, "illegal table size %#llx\n",
   347					(unsigned long long)table_size);
   348				return -EINVAL;
   349			}
   350	
   351			table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET;
   352			writel_relaxed(lower_32_bits(cpu_addr) |
   353					PCIE_ATR_SIZE(fls64(table_size) - 1), table);
   354			writel_relaxed(upper_32_bits(cpu_addr), table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
   355			writel_relaxed(lower_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
   356			writel_relaxed(upper_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
   357	
   358			if (type == IORESOURCE_IO) {
   359				val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
   360				range_type = "IO";
   361			} else {
   362				val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
   363				range_type = "MEM";
   364			}
   365	
   366			writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
   367	
   368			dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",
   369				range_type, *num, (unsigned long long)cpu_addr,
   370				(unsigned long long)pci_addr,
   371				(unsigned long long)table_size);
   372	
   373			cpu_addr += table_size;
   374			pci_addr += table_size;
   375			remaining -= table_size;
   376			(*num)++;
   377		}
   378	
   379		if (remaining)
   380			dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",
   381				 (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES);
   382	
   383		return 0;
   384	}
   385	

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