From: Jakub Kicinski <kuba@kernel.org>
To: Daniel Pawlik <pawlik.dan@gmail.com>
Cc: netdev@vger.kernel.org, lorenzo@kernel.org, win847@gmail.com,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v8] net: airoha: npu: use cacheline-sized buffers for mailbox DMA
Date: Thu, 20 Aug 2026 10:18:51 -0700 [thread overview]
Message-ID: <20260820101851.0b4c284a@kernel.org> (raw)
In-Reply-To: <CALC2ApiCSY8DkVpd7puTssbJZMWBHGVtFCnG66fiK0PX7-u3Hw@mail.gmail.com>
On Thu, 20 Aug 2026 10:20:08 +0200 Daniel Pawlik wrote:
> size=24 < cache_line=64 fails this regardless of address alignment.
> The swiotlb sync code itself is fine, but the NPU cannot DMA-write to
> the bounce buffer address range (it reads commands fine, never writes
> responses back). This is probably an EN7581 platform limitation.
Sure, that's pretty much what GPT told us some revisions ago.
The question is why.
prev parent reply other threads:[~2026-08-20 17:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-17 9:06 [PATCH v8] net: airoha: npu: use cacheline-sized buffers for mailbox DMA Daniel Pawlik
2026-08-17 9:52 ` Qingfang Deng
2026-08-17 23:17 ` Jakub Kicinski
2026-08-18 6:23 ` Daniel Pawlik
2026-08-18 15:29 ` Jakub Kicinski
2026-08-19 12:27 ` Daniel Pawlik
2026-08-20 8:20 ` Daniel Pawlik
2026-08-20 17:18 ` Jakub Kicinski [this message]
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