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Fri, 11 Sep 2026 23:40:57 -0700 (PDT) Received: from [192.168.18.164] ([2600:8804:5716:d800::b712]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-803f670ec82sm4932735a34.20.2026.09.11.23.40.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 23:40:56 -0700 (PDT) From: Ryan Brue Date: Sat, 12 Sep 2026 01:40:37 -0500 Subject: [PATCH 1/2] clk: mediatek: mt8173: fix the FHCTL DDS mask width MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260912-mt8173-fix-dds-mask-width-v1-1-3d0c0292c85c@gmail.com> References: <20260912-mt8173-fix-dds-mask-width-v1-0-3d0c0292c85c@gmail.com> In-Reply-To: <20260912-mt8173-fix-dds-mask-width-v1-0-3d0c0292c85c@gmail.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno , Chen-Yu Tsai Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Ryan Brue X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789195251; l=1697; i=ryanbrue.dev@gmail.com; s=20260906; h=from:subject:message-id; bh=rK3LI6EEJl+1gc/J0Nqb7f1MnKq7lREyQo2mSnW3Hpw=; b=aEEsL7VWo3CfcnRgQNR4pSp2BW0HTS7IMmCb+Oc21O48+SIoUTLwp4mzW8r7juB7bII0JxlDE J6mym376UJXBuM4QPyxPLfo+9VhIWv/sGKsTw5ZFgYRdJ6Q1/Kq1x2Y X-Developer-Key: i=ryanbrue.dev@gmail.com; a=ed25519; pk=KsUvVaP//v/2q+ZBuacc7cLbsyEYn+AD71Sn28oZWKo= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260911_234058_679548_66BDEE50 X-CRM114-Status: GOOD ( 12.89 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org MT8173's hoppable PLLs have pcwbits = 21, so the FHCTL DDS field is bits 20:0, but FH() declares .dds_mask = GENMASK(21, 0). Bit 21 of FHCTL_MON is a status bit that comes up once a hop has settled, and new_dds from mtk_pll_calc_values() is always 21-bit, so the poll in hopping_hw_flow() never matches and every hop runs to the 1000 us timeout. The PLL does reach the requested rate and clk_change_rate() discards the error, so the cost is 1 ms of atomic polling plus a warning and a register dump on each rate change. Six MMPLL rate changes on an Amazon Fire HD 10 (2017) all time out with GENMASK(21, 0), MON reading the requested DDS with bit 21 set, and all pass with GENMASK(20, 0). mt8186, mt8192 and mt8195 share the constant but are correct, as their hoppable PLLs really are 22-bit. mt6795 is fixed in the next patch. Fixes: 45a5cbe05d1f ("clk: mediatek: mt8173: Add support for frequency hopping through FHCTL") Assisted-by: LLM Signed-off-by: Ryan Brue --- drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c index d7d416172ab3..327240cd34fb 100644 --- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c @@ -100,7 +100,7 @@ enum fh_pll_id { .fh_id = _fhid, \ .fh_ver = FHCTL_PLLFH_V1, \ .fhx_offset = _offset, \ - .dds_mask = GENMASK(21, 0), \ + .dds_mask = GENMASK(20, 0), \ .slope0_value = 0x6003c97, \ .slope1_value = 0x6003c97, \ .sfstrx_en = BIT(2), \ -- 2.55.0