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Fri, 11 Sep 2026 23:41:00 -0700 (PDT) Received: from [192.168.18.164] ([2600:8804:5716:d800::b712]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-803f670ec82sm4932735a34.20.2026.09.11.23.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 23:40:58 -0700 (PDT) From: Ryan Brue Date: Sat, 12 Sep 2026 01:40:38 -0500 Subject: [PATCH 2/2] clk: mediatek: mt6795: fix the FHCTL DDS mask width MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260912-mt8173-fix-dds-mask-width-v1-2-3d0c0292c85c@gmail.com> References: <20260912-mt8173-fix-dds-mask-width-v1-0-3d0c0292c85c@gmail.com> In-Reply-To: <20260912-mt8173-fix-dds-mask-width-v1-0-3d0c0292c85c@gmail.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno , Chen-Yu Tsai Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Ryan Brue X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789195251; l=1440; i=ryanbrue.dev@gmail.com; s=20260906; h=from:subject:message-id; bh=Ql7C35Wo0Afw/TL/lX4BfvZeI5ogoZo8Mi0/Jvy5M00=; b=5WZnSsxv7VZ//QziiPqa/hfbDelv6xL9htaBXcHAb3pfvm74cL65FXg1wRmpJjS+un+7XrxzR 0b1Eg+HGMxLDS2ChLkM0XQoGJWSx9crrUYJwUWFswZOuImDIHOPypUz X-Developer-Key: i=ryanbrue.dev@gmail.com; a=ed25519; pk=KsUvVaP//v/2q+ZBuacc7cLbsyEYn+AD71Sn28oZWKo= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260911_234101_063678_811FB24B X-CRM114-Status: GOOD ( 12.54 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org All eight PLLs in mt6795's pllfhs[] have pcwbits = 21, so the FHCTL DDS field is bits 20:0, but _FH() declares .dds_mask = GENMASK(21, 0). As on MT8173, new_dds from mtk_pll_calc_values() is always 21-bit, so admitting bit 21 of FHCTL_MON into the poll in hopping_hw_flow() can only make it time out. The same mask feeds the CON1 write-back and fhctl_set_ssc_regs(). Unlike MT8173 this path has a user: mt6795-sony-xperia-m5.dts switches FHCTL on for mainpll, mpll and msdcpll, with SSC. Found by inspection while fixing MT8173. I have no MT6795 hardware, so this one is untested. Fixes: f222a1baec5f ("clk: mediatek: mt6795: Add support for frequency hopping through FHCTL") Assisted-by: LLM Signed-off-by: Ryan Brue --- drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c index 123d5d7fea85..ff01cfefc31f 100644 --- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c @@ -79,7 +79,7 @@ enum fh_pll_id { .fh_id = _fhid, \ .fh_ver = FHCTL_PLLFH_V1, \ .fhx_offset = _offset, \ - .dds_mask = GENMASK(21, 0), \ + .dds_mask = GENMASK(20, 0), \ .slope0_value = _slope, \ .slope1_value = _slope, \ .sfstrx_en = BIT(2), \ -- 2.55.0