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Wysocki" , Danilo Krummrich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , linux-acpi@vger.kernel.org, driver-core@lists.linux.dev, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Alan Stern , Bartosz Golaszewski Subject: [PATCH v9 14/15] arm64: dts: mediatek: mt8195-cherry: Add M.2 E-key slot Date: Wed, 16 Sep 2026 15:57:40 +0800 Message-ID: <20260916075745.3549953-15-wenst@chromium.org> X-Mailer: git-send-email 2.55.0.1032.g73a4cd73de-goog In-Reply-To: <20260916075745.3549953-1-wenst@chromium.org> References: <20260916075745.3549953-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260916_005937_653145_B57B18C2 X-CRM114-Status: GOOD ( 14.40 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The Mt8195 Cherry design features an M.2 E-key slot for WiFi/BT combo cards. Only PCIe and USB are wired from the SoC to the slot, along with some auxiliary signals. Add the proper representation for it, replacing the PCIe wifi node and vpcie3v3-supply property under the PCIe controller, and the vbus-supply property under the xhci3 node. Reviewed-by: Bartosz Golaszewski Signed-off-by: Chen-Yu Tsai --- Changes since v2: - Drop default GPIO output state from kill pins pinconfig --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 73 +++++++++++++++++-- 1 file changed, 68 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index f06ca2bc165d..5d65f4554c6e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -271,6 +271,47 @@ tboard_thermistor2: thermal-sensor-t2 { 120000 51 125000 44>; }; + + wifi-bt-connector { + compatible = "pcie-m2-e-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&m2_e_key_kill_pins>; + vpcie3v3-supply = <&pp3300_wlan>; + w-disable1-gpios = <&pio 61 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&pio 59 GPIO_ACTIVE_LOW>; + /* PCIe auxiliary signals wired to controller. */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* PCIe for WiFi */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + wifi_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie1_ep>; + }; + }; + + /* USB for Bluetooth */ + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + bt_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&usb3_ep>; + }; + }; + + /* SDIO, UART and I2S not implemented */ + }; + }; }; &adsp { @@ -796,14 +837,14 @@ pcie@0 { reg = <0 0 0 0 0>; device_type = "pci"; num-lanes = <1>; - vpcie3v3-supply = <&pp3300_wlan>; #address-cells = <3>; #size-cells = <2>; ranges; - wifi@0 { - reg = <0 0 0 0 0>; - wakeup-source; + port { + pcie1_ep: endpoint { + remote-endpoint = <&wifi_ep>; + }; }; }; }; @@ -1090,6 +1131,13 @@ pins-bus { }; }; + m2_e_key_kill_pins: m2-e-key-kill-pins { + pins-kill { + pinmux = , + ; + }; + }; + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux = , @@ -1642,9 +1690,24 @@ &xhci2 { &xhci3 { /* MT7921's USB Bluetooth has issues with USB2 LPM */ usb2-lpm-disable; - vbus-supply = <&pp3300_wlan>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&bt_ep>; + }; + }; + }; }; #include -- 2.55.0.1032.g73a4cd73de-goog