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Wed, 16 Sep 2026 00:59:40 -0700 (PDT) Received: from wenst-7875.tpe.corp.google.com ([2a00:79e0:203d:7:1f62:7622:5d61:2578]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e1b7acba2sm4348197a91.16.2026.09.16.00.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2026 00:59:40 -0700 (PDT) From: Chen-Yu Tsai To: Bartosz Golaszewski , Greg Kroah-Hartman , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , "Rafael J. Wysocki" , Danilo Krummrich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , linux-acpi@vger.kernel.org, driver-core@lists.linux.dev, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Alan Stern , Bartosz Golaszewski Subject: [PATCH v9 15/15] arm64: dts: mediatek: mt8188-geralt: Add WiFi/BT as M.2 E-key slot Date: Wed, 16 Sep 2026 15:57:41 +0800 Message-ID: <20260916075745.3549953-16-wenst@chromium.org> X-Mailer: git-send-email 2.55.0.1032.g73a4cd73de-goog In-Reply-To: <20260916075745.3549953-1-wenst@chromium.org> References: <20260916075745.3549953-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260916_085943_037853_95C23A02 X-CRM114-Status: GOOD ( 16.60 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The MT8188 Geralt design features a chip-on-board WiFi/BT solution. This is a M.2 E-key WiFi/BT board layout directly inserted into the mainboard design. The connections to the rest of the board are almost the same as if it were a separate M.2 card. The only addition is the PMU_EN pin on the chip; on M.2 cards this would be tied to the primary power source. Model the chip-on-board WiFi/BT solution as a M.2 E-key slot with PCIe, USB and auxiliary signals. The PMU_EN pin, which enables the internal power controls and regulators, is modeled as a regulator fed by the pp3300_wlan regulator. Since power sequencing is now correctly modeled using the M.2 E-key slot, drop the "regulator-always-on" property one pp3300_wlan regulator. Also drop the comment in xhci2 saying "MT7921's power is controlled by PCIe". Also drop the voltage range on the pp3300_wlan regulator. This "regulator" is just a load switch and does not provide any regulation. Reviewed-by: Bartosz Golaszewski Signed-off-by: Chen-Yu Tsai --- Changes since v2: - Drop default GPIO output state from kill pins pinconfig --- .../boot/dts/mediatek/mt8188-geralt.dtsi | 92 ++++++++++++++++++- 1 file changed, 88 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index ba3dcfc50956..4704abaebcf8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -93,13 +93,11 @@ pp3300_z1: regulator-pp3300-z1 { pp3300_wlan: regulator-pp3300-wlan { compatible = "regulator-fixed"; regulator-name = "pp3300_wlan"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; enable-active-high; gpio = <&pio 12 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&wlan_en>; pinctrl-names = "default"; + /* load switch */ vin-supply = <&pp3300_z1>; }; @@ -166,6 +164,17 @@ ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee { vin-supply = <&pp5000_z1>; }; + /* PMU_EN pin controls internal regulators and power sequence */ + wlan_pmu: regulator-wlan-pmu { + compatible = "regulator-fixed"; + regulator-name = "wlan-pmu"; + enable-active-high; + gpio = <&pio 145 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wlan_pmu_en>; + pinctrl-names = "default"; + vin-supply = <&pp3300_wlan>; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -200,6 +209,39 @@ adsp_dma_mem: memory@61000000 { no-map; }; }; + + wifi-bt-connector { + compatible = "pcie-m2-e-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&m2_e_key_kill_pins>; + vpcie1v8-supply = <&mt6359_vcn18_ldo_reg>; + vpcie3v3-supply = <&wlan_pmu>; + w-disable1-gpios = <&pio 13 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&pio 14 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* PCIe for WiFi */ + port@0 { + reg = <0>; + + wifi_ep: endpoint { + remote-endpoint = <&pcie_ep>; + }; + }; + + /* USB for Bluetooth */ + port@2 { + reg = <2>; + + bt_ep: endpoint { + remote-endpoint = <&usb2_ep>; + }; + }; + }; + }; }; &adsp { @@ -664,6 +706,22 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; status = "okay"; + + pcie@0 { + compatible = "pciclass,0604"; + reg = <0 0 0 0 0>; + device_type = "pci"; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + port { + pcie_ep: endpoint { + remote-endpoint = <&wifi_ep>; + }; + }; + }; }; &pciephy { @@ -1007,6 +1065,13 @@ pins-bus { }; }; + m2_e_key_kill_pins: m2-e-key-kill-pins { + pins-kill { + pinmux = , + ; + }; + }; + mipi_disp_avdd_en: mipi-disp-avdd-en-pins { pins-en-ppvar-mipi-disp { pinmux = ; @@ -1179,6 +1244,13 @@ pins-bus { }; }; + wlan_pmu_en: wlan-pmu-en-pins { + pins-wlan-pmu-en { + pinmux = ; + output-low; + }; + }; + wlan_en: wlan-en-pins { pins-en-pp3300-wlan { pinmux = ; @@ -1422,10 +1494,22 @@ vdosys1_ep_ext: endpoint@1 { }; &xhci2 { - /* no power supply since MT7921's power is controlled by PCIe */ /* MT7921's USB BT has issues with USB2 LPM */ usb2-lpm-disable; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb2_ep: endpoint { + remote-endpoint = <&bt_ep>; + }; + }; + }; }; #include -- 2.55.0.1032.g73a4cd73de-goog