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Fri, 18 Sep 2026 10:57:51 -0700 (PDT) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48724562aebsm268461f8f.14.2026.09.18.10.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 10:57:50 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/4] soc: mediatek: mt8167-mmsys: add routes for all display paths Date: Fri, 18 Sep 2026 19:55:27 +0200 Message-ID: <20260918175736.355305-4-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918175736.355305-1-l.scorcia@gmail.com> References: <20260918175736.355305-1-l.scorcia@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260918_105753_040024_6CFC635B X-CRM114-Status: GOOD ( 14.35 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org mt8167 display output pipeline can be configured in many different ways. Add support for additional routes according to the SoC data sheet and Android sources. There's a few inconsistencies between those two, but assume the Android sources are correct since they are required to drive HDMI output via DPI1. Signed-off-by: Luca Leonardo Scorcia --- drivers/soc/mediatek/mt8167-mmsys.h | 183 ++++++++++++++++++++++++++-- 1 file changed, 174 insertions(+), 9 deletions(-) diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h index 001379373507..aab1774152c5 100644 --- a/drivers/soc/mediatek/mt8167-mmsys.h +++ b/drivers/soc/mediatek/mt8167-mmsys.h @@ -5,35 +5,200 @@ #define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030 #define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038 +#define MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x03c #define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x058 +#define MT8167_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN 0x05c +#define MT8167_DISP_REG_CONFIG_DISP_UFOE_SEL_IN 0x060 #define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0x064 +#define MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0x068 #define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x06c +#define MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN 0x070 +#define MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN 0x074 + +#define MT8167_OVL0_MOUT_EN_COLOR0 0x1 +#define MT8167_OVL0_MOUT_EN_WDMA0 0x2 +#define MT8167_OVL0_MOUT_EN_MASK 0x3 #define MT8167_DITHER_MOUT_EN_RDMA0 0x1 +#define MT8167_DITHER_MOUT_EN_UFOE 0x2 +#define MT8167_DITHER_MOUT_EN_WDMA0 0x4 #define MT8167_DITHER_MOUT_EN_MASK 0x7 -#define MT8167_RDMA0_SOUT_DSI0 0x2 -#define MT8167_RDMA0_SOUT_MASK 0x3 +#define MT8167_UFOE_MOUT_EN_DSI0 0x1 +#define MT8167_UFOE_MOUT_EN_DPI0 0x2 +/* + * For some reason Android sources and the data sheet don't agree here, + * the data sheet has UFOE_MOUT_EN_WDMA0 as 0x4 and does not mention DPI1. + */ +#define MT8167_UFOE_MOUT_EN_DPI1 0x4 +#define MT8167_UFOE_MOUT_EN_WDMA0 0x8 +#define MT8167_UFOE_MOUT_EN_MASK 0xF + +#define MT8167_COLOR0_SEL_IN_RDMA0 0x0 +#define MT8167_COLOR0_SEL_IN_OVL0 0x1 +#define MT8167_COLOR0_SEL_IN_MASK 0x1 + +#define MT8167_WDMA0_SEL_IN_OVL0 0x0 +#define MT8167_WDMA0_SEL_IN_DITHER 0x1 +#define MT8167_WDMA0_SEL_IN_UFOE 0x2 +#define MT8167_WDMA0_SEL_IN_MASK 0x3 + +#define MT8167_UFOE_SEL_IN_RDMA0 0x0 +#define MT8167_UFOE_SEL_IN_DITHER 0x1 +#define MT8167_UFOE_SEL_IN_MASK 0x1 +#define MT8167_DSI0_SEL_IN_UFOE 0x0 #define MT8167_DSI0_SEL_IN_RDMA0 0x1 +#define MT8167_DSI0_SEL_IN_RDMA1 0x2 #define MT8167_DSI0_SEL_IN_MASK 0x3 +#define MT8167_DPI0_SEL_IN_UFOE 0x0 +#define MT8167_DPI0_SEL_IN_RDMA0 0x1 +#define MT8167_DPI0_SEL_IN_RDMA1 0x2 +#define MT8167_DPI0_SEL_IN_MASK 0x3 + +#define MT8167_DPI1_SEL_IN_UFOE 0x0 +#define MT8167_DPI1_SEL_IN_RDMA0 0x1 +#define MT8167_DPI1_SEL_IN_RDMA1 0x2 +#define MT8167_DPI1_SEL_IN_MASK 0x3 + +#define MT8167_RDMA0_SOUT_UFOE 0x0 +#define MT8167_RDMA0_SOUT_COLOR0 0x1 +#define MT8167_RDMA0_SOUT_DSI0 0x2 +#define MT8167_RDMA0_SOUT_DPI0 0x3 +/* DPI1 is only defined in Android sources, not in the data sheet */ +#define MT8167_RDMA0_SOUT_DPI1 0x4 +#define MT8167_RDMA0_SOUT_MASK 0x7 + +#define MT8167_RDMA1_SOUT_DSI0 0x0 +#define MT8167_RDMA1_SOUT_DPI0 0x1 +/* DPI1 is only defined in Android sources, not in the data sheet */ +#define MT8167_RDMA1_SOUT_DPI1 0x2 +#define MT8167_RDMA1_SOUT_MASK 0x3 + static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { + /* OVL0<->COLOR0 */ MMSYS_ROUTE(OVL, 0, COLOR, 0, - MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, - OVL0_MOUT_EN_COLOR0), + MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8167_OVL0_MOUT_EN_MASK, + MT8167_OVL0_MOUT_EN_COLOR0), + MMSYS_ROUTE(OVL, 0, COLOR, 0, + MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK, + MT8167_COLOR0_SEL_IN_OVL0), + + /* OVL0<->WDMA0 */ + MMSYS_ROUTE(OVL, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8167_OVL0_MOUT_EN_MASK, + MT8167_OVL0_MOUT_EN_WDMA0), + MMSYS_ROUTE(OVL, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK, + MT8167_WDMA0_SEL_IN_OVL0), + + /* DITHER0 outputs */ MMSYS_ROUTE(DITHER, 0, RDMA, 0, MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK, MT8167_DITHER_MOUT_EN_RDMA0), - MMSYS_ROUTE(OVL, 0, COLOR, 0, - MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0, - COLOR0_SEL_IN_OVL0), - MMSYS_ROUTE(RDMA, 0, DSI, 0, + MMSYS_ROUTE(DITHER, 0, UFOE, 0, + MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK, + MT8167_DITHER_MOUT_EN_UFOE), + MMSYS_ROUTE(DITHER, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK, + MT8167_DITHER_MOUT_EN_WDMA0), + + /* UFOE<->DSI0 */ + MMSYS_ROUTE(UFOE, 0, DSI, 0, + MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK, + MT8167_UFOE_MOUT_EN_DSI0), + MMSYS_ROUTE(UFOE, 0, DSI, 0, MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK, - MT8167_DSI0_SEL_IN_RDMA0), + MT8167_DSI0_SEL_IN_UFOE), + + /* UFOE<->DPI0 */ + MMSYS_ROUTE(UFOE, 0, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK, + MT8167_UFOE_MOUT_EN_DPI0), + MMSYS_ROUTE(UFOE, 0, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK, + MT8167_DPI0_SEL_IN_UFOE), + + /* UFOE<->DPI1 */ + MMSYS_ROUTE(UFOE, 0, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK, + MT8167_UFOE_MOUT_EN_DPI1), + MMSYS_ROUTE(UFOE, 0, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK, + MT8167_DPI1_SEL_IN_UFOE), + + /* UFOE<->WDMA0 */ + MMSYS_ROUTE(UFOE, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK, + MT8167_UFOE_MOUT_EN_WDMA0), + MMSYS_ROUTE(UFOE, 0, WDMA, 0, + MT8167_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN, MT8167_WDMA0_SEL_IN_MASK, + MT8167_WDMA0_SEL_IN_UFOE), + + /* RDMA0<->UFOE */ + MMSYS_ROUTE(RDMA, 0, UFOE, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK, + MT8167_RDMA0_SOUT_UFOE), + MMSYS_ROUTE(RDMA, 0, UFOE, 0, + MT8167_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8167_UFOE_SEL_IN_MASK, + MT8167_UFOE_SEL_IN_RDMA0), + + /* RDMA0->COLOR0 */ + MMSYS_ROUTE(RDMA, 0, COLOR, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK, + MT8167_RDMA0_SOUT_COLOR0), + MMSYS_ROUTE(RDMA, 0, COLOR, 0, + MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK, + MT8167_COLOR0_SEL_IN_RDMA0), + + /* RDMA0<->DSI0 */ MMSYS_ROUTE(RDMA, 0, DSI, 0, MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK, MT8167_RDMA0_SOUT_DSI0), + MMSYS_ROUTE(RDMA, 0, DSI, 0, + MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK, + MT8167_DSI0_SEL_IN_RDMA0), + + /* RDMA0<->DPI0 */ + MMSYS_ROUTE(RDMA, 0, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK, + MT8167_RDMA0_SOUT_DPI0), + MMSYS_ROUTE(RDMA, 0, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK, + MT8167_DPI0_SEL_IN_RDMA0), + + /* RDMA0<->DPI1 */ + MMSYS_ROUTE(RDMA, 0, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK, + MT8167_RDMA0_SOUT_DPI1), + MMSYS_ROUTE(RDMA, 0, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK, + MT8167_DPI1_SEL_IN_RDMA0), + + /* RDMA1<->DSI0 */ + MMSYS_ROUTE(RDMA, 1, DSI, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MASK, + MT8167_RDMA1_SOUT_DSI0), + MMSYS_ROUTE(RDMA, 1, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK, + MT8167_DPI0_SEL_IN_RDMA1), + + /* RDMA1<->DPI0 */ + MMSYS_ROUTE(RDMA, 1, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MASK, + MT8167_RDMA1_SOUT_DPI0), + MMSYS_ROUTE(RDMA, 1, DPI, 0, + MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK, + MT8167_DPI0_SEL_IN_RDMA1), + + /* RDMA1<->DPI1 */ + MMSYS_ROUTE(RDMA, 1, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MASK, + MT8167_RDMA1_SOUT_DPI1), + MMSYS_ROUTE(RDMA, 1, DPI, 1, + MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK, + MT8167_DPI1_SEL_IN_RDMA1), }; #endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */ -- 2.43.0