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Mon, 21 Sep 2026 03:25:40 -0700 (PDT) Received: from buffalo-ssd.taila54753.ts.net ([240b:253:4760:f400:1ebf:ceff:fe7f:5e0b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-877a94f238csm2909174b3a.21.2026.09.21.03.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 03:25:40 -0700 (PDT) From: Akari Tsuyukusa To: Stephen Boyd , Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno Cc: Takashi Sakamoto , Danilo Krummrich , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Bjorn Helgaas , Akari Tsuyukusa , Nicolas Frattaroli , Chen-Yu Tsai , Laura Nao , Sjoerd Simons , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 4/6] clk: mediatek: Reserve missing MT8173 topckgen IDs Date: Mon, 21 Sep 2026 19:25:20 +0900 Message-ID: <20260921102522.1640072-5-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921102522.1640072-1-akkun11.open@gmail.com> References: <20260921102522.1640072-1-akkun11.open@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260921_032541_439843_4AA78345 X-CRM114-Status: UNSURE ( 9.63 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Reserve the unused clock ID 2 and the binding-defined CLK_TOP_HDMITX_DIG_CTS slot in the MT8173 topckgen provider. Neither clock is implemented by topckgen: ID 2 corresponds to the removed DPI clock, while the HDMI digital clock is provided by the HDMI PHY. Keep both onecell slots populated with dummy clocks so the descriptor-based allocation covers the complete registered ID range. Assisted-by: GPT-5.6 Luna Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8173-topckgen.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8173-topckgen.c b/drivers/clk/mediatek/clk-mt8173-topckgen.c index 42c37541cebb..9c50f66766b4 100644 --- a/drivers/clk/mediatek/clk-mt8173-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8173-topckgen.c @@ -624,6 +624,11 @@ static const struct mtk_composite top_muxes[] = { MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), }; +static const struct mtk_gate top_dummy_clks[] = { + GATE_DUMMY(2, "topck_reserved_2"), + GATE_DUMMY(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts_dummy"), +}; + static const struct mtk_clk_desc topck_desc = { .fixed_clks = fixed_clks, .num_fixed_clks = ARRAY_SIZE(fixed_clks), @@ -631,6 +636,8 @@ static const struct mtk_clk_desc topck_desc = { .num_factor_clks = ARRAY_SIZE(top_divs), .composite_clks = top_muxes, .num_composite_clks = ARRAY_SIZE(top_muxes), + .clks = top_dummy_clks, + .num_clks = ARRAY_SIZE(top_dummy_clks), .clk_lock = &mt8173_top_clk_lock, }; -- 2.55.0