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Mon, 21 Sep 2026 04:39:33 -0700 (PDT) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fc57547easm244273865e9.3.2026.09.21.04.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 04:39:32 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/4] arm64: dts: mediatek: mt8167: Add DRM nodes Date: Mon, 21 Sep 2026 13:38:58 +0200 Message-ID: <20260921113914.779393-5-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921113914.779393-1-l.scorcia@gmail.com> References: <20260921113914.779393-1-l.scorcia@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260921_123940_459023_AC04DD40 X-CRM114-Status: UNSURE ( 9.74 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add all the DRM nodes required to get DSI and DPI to work on MT8167 SoC. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 369 +++++++++++++++++++++++ 1 file changed, 369 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 27cf32d7ae35..a50bae4307c1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -16,6 +16,22 @@ / { compatible = "mediatek,mt8167"; + aliases { + aal0 = &aal; + ccorr0 = &ccorr; + color0 = &color; + dither0 = &dither; + dpi0 = &dpi0; + dpi1 = &dpi1; + dsi0 = &dsi; + gamma0 = γ + ovl0 = &ovl0; + pwm0 = &disp_pwm; + rdma0 = &rdma0; + rdma1 = &rdma1; + wdma0 = &wdma; + }; + soc { topckgen: topckgen@10000000 { compatible = "mediatek,mt8167-topckgen", "syscon"; @@ -120,10 +136,325 @@ iommu: m4u@10203000 { #iommu-cells = <1>; }; + disp_pwm: pwm@1100f000 { + compatible = "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm"; + reg = <0 0x1100f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_PWM_26M>, <&mmsys CLK_MM_DISP_PWM_MM>; + clock-names = "main", "mm"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + status = "disabled"; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; #clock-cells = <1>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + + mmsys_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_in>; + }; + }; + }; + + ovl0: ovl0@14007000 { + compatible = "mediatek,mt8167-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { + remote-endpoint = <&mmsys_main>; + }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&color_in>; + }; + }; + }; + }; + + rdma0: rdma0@14009000 { + compatible = "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg = <0 0x14009000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&dither_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { }; + }; + }; + }; + + rdma1: rdma1@1400a000 { + compatible = "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg = <0 0x1400a000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma1_in: endpoint { + remote-endpoint = <&mmsys_ext>; + }; + }; + + port@1 { + reg = <1>; + rdma1_out: endpoint { }; + }; + }; + }; + + wdma: wdma0@1400b000 { + compatible = "mediatek,mt8167-disp-wdma", "mediatek,mt8173-disp-wdma"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_WDMA0>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + color: color@1400c000 { + compatible = "mediatek,mt8167-disp-color"; + reg = <0 0x1400c000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + color_out: endpoint { + remote-endpoint = <&ccorr_in>; + }; + }; + }; + }; + + ccorr: ccorr@1400d000 { + compatible = "mediatek,mt8167-disp-ccorr", "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_CCORR>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr_in: endpoint { + remote-endpoint = <&color_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr_out: endpoint { + remote-endpoint = <&aal_in>; + }; + }; + }; + }; + + aal: aal@1400e000 { + compatible = "mediatek,mt8167-disp-aal", "mediatek,mt8173-disp-aal"; + reg = <0 0x1400e000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_AAL>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal_in: endpoint { + remote-endpoint = <&ccorr_out>; + }; + }; + + port@1 { + reg = <1>; + aal_out: endpoint { + remote-endpoint = <&gamma_in>; + }; + }; + }; + }; + + gamma: gamma@1400f000 { + compatible = "mediatek,mt8167-disp-gamma", "mediatek,mt8173-disp-gamma"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma_in: endpoint { + remote-endpoint = <&aal_out>; + }; + }; + + port@1 { + reg = <1>; + gamma_out: endpoint { + remote-endpoint = <&dither_in>; + }; + }; + }; + }; + + dither: dither@14010000 { + compatible = "mediatek,mt8167-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_DITHER>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither_in: endpoint { + remote-endpoint = <&gamma_out>; + }; + }; + + port@1 { + reg = <1>; + dither_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; + }; + + dsi: dsi@14012000 { + compatible = "mediatek,mt8167-dsi"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIGITAL>, + <&mipi_tx>; + clock-names = "engine", "digital", "hs"; + interrupts = ; + phys = <&mipi_tx>; + phy-names = "dphy"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { }; + }; + }; + }; + + dpi0: dpi@14013000 { + compatible = "mediatek,mt8167-dpi"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_DPI0_PXL>, <&mmsys CLK_MM_DPI0_ENGINE>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names = "pixel", "engine", "pll"; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dpi0_out: endpoint { }; + }; + }; + }; + + mutex: mutex@14015000 { + compatible = "mediatek,mt8167-disp-mutex"; + reg = <0 0x14015000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; larb0: larb@14016000 { @@ -145,6 +476,44 @@ smi_common: smi@14017000 { power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; + mipi_tx: dsi-phy@14018000 { + compatible = "mediatek,mt8167-mipi-tx", "mediatek,mt2701-mipi-tx"; + reg = <0 0x14018000 0 0x90>; + clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + dpi1: dpi1@14019000 { + compatible = "mediatek,mt8167-dpi"; + reg = <0 0x14019000 0 0x1000>; + clocks = <&mmsys CLK_MM_DPI1_PXL>, <&mmsys CLK_MM_DPI1_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi1_in: endpoint { }; + }; + + port@1 { + reg = <1>; + + dpi1_out: endpoint { }; + }; + }; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt8167-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- 2.43.0