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[79.29.83.136]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49ff06cbe57sm12288175e9.13.2026.09.24.16.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 16:02:58 -0700 (PDT) From: Christian Marangi To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan , Randy Dunlap , Christian Marangi , Lorenzo Bianconi , Heiner Kallweit , Russell King , Philipp Zabel , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, llvm@lists.linux.dev Cc: Zhengping Zhang Subject: [PATCH net-next v17 12/12] net: airoha: add phylink support Date: Fri, 25 Sep 2026 01:01:53 +0200 Message-ID: <20260924230211.11519-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260924230211.11519-1-ansuelsmth@gmail.com> References: <20260924230211.11519-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260925_000300_734904_1118CA7A X-CRM114-Status: GOOD ( 26.33 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add phylink support for each GDM port. For GDM1 add the internal interface mode as the only supported mode. For GDM2/3/4 add the required configuration of the PCS to make the external PHY or attached SFP cage work. These needs to be defined in the GDM port node using the pcs-handle property. Update and provide a .get/set_link_ksettings function that use phylink for ethtool OPs now that we fully support phylink. Tested-by: Zhengping Zhang Acked-by: Lorenzo Bianconi Signed-off-by: Christian Marangi --- drivers/net/ethernet/airoha/Kconfig | 2 + drivers/net/ethernet/airoha/airoha_eth.c | 197 +++++++++++++++++++++- drivers/net/ethernet/airoha/airoha_eth.h | 5 + drivers/net/ethernet/airoha/airoha_regs.h | 12 ++ 4 files changed, 213 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/airoha/Kconfig b/drivers/net/ethernet/airoha/Kconfig index 1f6640a15fc9..5c54a07d2a76 100644 --- a/drivers/net/ethernet/airoha/Kconfig +++ b/drivers/net/ethernet/airoha/Kconfig @@ -20,6 +20,8 @@ config NET_AIROHA depends on NET_DSA || !NET_DSA select NET_AIROHA_NPU select PAGE_POOL + select PCS_AIROHA + select PHYLINK help This driver supports the gigabit ethernet MACs in the Airoha SoC family. diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c index 21ac80bdd084..45e99cc8dbf3 100644 --- a/drivers/net/ethernet/airoha/airoha_eth.c +++ b/drivers/net/ethernet/airoha/airoha_eth.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -2194,10 +2195,18 @@ static int airoha_dev_open(struct net_device *netdev) return -EBUSY; } + err = phylink_of_phy_connect(dev->phylink, netdev->dev.of_node, 0); + if (err) { + netdev_err(netdev, "could not attach PHY: %d\n", err); + return err; + } + + phylink_start(dev->phylink); + netif_tx_start_all_queues(netdev); err = airoha_set_vip_for_gdm_port(dev, true); if (err) - return err; + goto err_phy_stop; if (netdev_uses_dsa(netdev)) airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id), @@ -2219,6 +2228,12 @@ static int airoha_dev_open(struct net_device *netdev) airoha_dev_lro_enable(dev); return 0; + +err_phy_stop: + phylink_stop(dev->phylink); + phylink_disconnect_phy(dev->phylink); + + return err; } static int airoha_dev_stop(struct net_device *netdev) @@ -2226,6 +2241,8 @@ static int airoha_dev_stop(struct net_device *netdev) struct airoha_gdm_dev *dev = netdev_priv(netdev); struct airoha_gdm_port *port = dev->port; + phylink_stop(dev->phylink); + netif_tx_disable(netdev); airoha_set_vip_for_gdm_port(dev, false); @@ -2239,6 +2256,8 @@ static int airoha_dev_stop(struct net_device *netdev) if (netdev->features & NETIF_F_LRO) airoha_dev_lro_disable(dev); + phylink_disconnect_phy(dev->phylink); + return 0; } @@ -2829,6 +2848,24 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev, } while (u64_stats_fetch_retry(&dev->stats.syncp, start)); } +static int +airoha_ethtool_get_link_ksettings(struct net_device *netdev, + struct ethtool_link_ksettings *cmd) +{ + struct airoha_gdm_dev *dev = netdev_priv(netdev); + + return phylink_ethtool_ksettings_get(dev->phylink, cmd); +} + +static int +airoha_ethtool_set_link_ksettings(struct net_device *netdev, + const struct ethtool_link_ksettings *cmd) +{ + struct airoha_gdm_dev *dev = netdev_priv(netdev); + + return phylink_ethtool_ksettings_set(dev->phylink, cmd); +} + static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev, int channel, enum tx_sched_mode mode, const u16 *weights, u8 n_weights) @@ -3676,7 +3713,8 @@ static const struct ethtool_ops airoha_ethtool_ops = { .get_drvinfo = airoha_ethtool_get_drvinfo, .get_eth_mac_stats = airoha_ethtool_get_mac_stats, .get_rmon_stats = airoha_ethtool_get_rmon_stats, - .get_link_ksettings = phy_ethtool_get_link_ksettings, + .get_link_ksettings = airoha_ethtool_get_link_ksettings, + .set_link_ksettings = airoha_ethtool_set_link_ksettings, .get_link = ethtool_op_get_link, }; @@ -3732,6 +3770,155 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth, return false; } +/* Nothing to do in MAC, everything is handled in PCS */ +static void airoha_mac_config(struct phylink_config *config, unsigned int mode, + const struct phylink_link_state *state) +{ +} + +static void airoha_mac_link_up(struct phylink_config *config, struct phy_device *phy, + unsigned int mode, phy_interface_t interface, + int speed, int duplex, bool tx_pause, bool rx_pause) +{ + struct airoha_gdm_dev *dev = container_of(config, struct airoha_gdm_dev, + phylink_config); + struct airoha_gdm_port *port = dev->port; + struct airoha_eth *eth = dev->eth; + u32 frag_size_tx, frag_size_rx; + + /* TX/RX frag is configured only for GDM4 */ + if (port->id != AIROHA_GDM4_IDX) + return; + + switch (speed) { + case SPEED_10000: + case SPEED_5000: + frag_size_tx = 8; + frag_size_rx = 8; + break; + case SPEED_2500: + frag_size_tx = 2; + frag_size_rx = 1; + break; + default: + frag_size_tx = 1; + frag_size_rx = 0; + break; + } + + mutex_lock(&port->link_lock); + + /* Configure TX/RX frag based on speed */ + if (dev->nbq == 1) { + airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG, + GDM4_SGMII1_TX_FRAG_SIZE_MASK, + FIELD_PREP(GDM4_SGMII1_TX_FRAG_SIZE_MASK, + frag_size_tx)); + + airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG, + GDM4_SGMII1_RX_FRAG_SIZE_MASK, + FIELD_PREP(GDM4_SGMII1_RX_FRAG_SIZE_MASK, + frag_size_rx)); + } else { + airoha_fe_rmw(eth, REG_FE_GDM4_TMBI_FRAG, + GDM4_SGMII0_TX_FRAG_SIZE_MASK, + FIELD_PREP(GDM4_SGMII0_TX_FRAG_SIZE_MASK, + frag_size_tx)); + + airoha_fe_rmw(eth, REG_FE_GDM4_RMBI_FRAG, + GDM4_SGMII0_RX_FRAG_SIZE_MASK, + FIELD_PREP(GDM4_SGMII0_RX_FRAG_SIZE_MASK, + frag_size_rx)); + } + + mutex_unlock(&port->link_lock); +} + +/* Nothing to do in MAC, everything is handled in PCS */ +static void airoha_mac_link_down(struct phylink_config *config, unsigned int mode, + phy_interface_t interface) +{ +} + +static const struct phylink_mac_ops airoha_phylink_ops = { + .mac_config = airoha_mac_config, + .mac_link_up = airoha_mac_link_up, + .mac_link_down = airoha_mac_link_down, +}; + +static int airoha_fill_available_pcs(struct phylink_config *config, + struct phylink_pcs **available_pcs, + unsigned int num_possible_pcs) +{ + struct device *dev = config->dev; + + return fwnode_phylink_pcs_parse(dev_fwnode(dev), available_pcs, + num_possible_pcs); +} + +static int airoha_setup_phylink(struct net_device *netdev) +{ + struct airoha_gdm_dev *dev = netdev_priv(netdev); + struct device_node *np = netdev->dev.of_node; + struct airoha_gdm_port *port = dev->port; + struct phylink_config *config; + phy_interface_t phy_mode; + struct phylink *phylink; + int err; + + err = of_get_phy_mode(np, &phy_mode); + if (err) { + dev_err(&netdev->dev, "incorrect phy-mode\n"); + return err; + } + + config = &dev->phylink_config; + config->dev = &netdev->dev; + config->type = PHYLINK_NETDEV; + + /* + * GDM1 only supports internal for Embedded Switch + * and doesn't require a PCS. + */ + if (port->id == AIROHA_GDM1_IDX) { + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10000FD; + + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + } else { + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000 | + MAC_2500FD | MAC_5000FD | MAC_10000FD; + + config->num_possible_pcs = fwnode_phylink_pcs_count(dev_fwnode(config->dev)); + config->fill_available_pcs = airoha_fill_available_pcs; + + __set_bit(PHY_INTERFACE_MODE_SGMII, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_10GBASER, + config->supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_USXGMII, + config->supported_interfaces); + + phy_interface_copy(config->pcs_interfaces, + config->supported_interfaces); + } + + phylink = phylink_create(config, of_fwnode_handle(np), + phy_mode, &airoha_phylink_ops); + if (IS_ERR(phylink)) + return PTR_ERR(phylink); + + dev->phylink = phylink; + + return 0; +} + static int airoha_alloc_gdm_device(struct airoha_eth *eth, struct airoha_gdm_port *port, int nbq, struct device_node *np) @@ -3795,7 +3982,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth, dev->nbq = nbq; port->devs[index] = dev; - return 0; + return airoha_setup_phylink(netdev); } static int airoha_alloc_gdm_port(struct airoha_eth *eth, @@ -3831,6 +4018,7 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth, port->id = id; spin_lock_init(&port->stats_lock); + mutex_init(&port->link_lock); eth->ports[p] = port; err = airoha_metadata_dst_alloc(port); @@ -4027,6 +4215,8 @@ static int airoha_probe(struct platform_device *pdev) netdev = netdev_from_priv(dev); if (netdev->reg_state == NETREG_REGISTERED) unregister_netdev(netdev); + if (dev->phylink) + phylink_destroy(dev->phylink); of_node_put(netdev->dev.of_node); } airoha_metadata_dst_free(port); @@ -4065,6 +4255,7 @@ static void airoha_remove(struct platform_device *pdev) netdev = netdev_from_priv(dev); unregister_netdev(netdev); + phylink_destroy(dev->phylink); of_node_put(netdev->dev.of_node); } airoha_metadata_dst_free(port); diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h index 286f73e2e1e0..7dd7c6beb7ca 100644 --- a/drivers/net/ethernet/airoha/airoha_eth.h +++ b/drivers/net/ethernet/airoha/airoha_eth.h @@ -610,6 +610,9 @@ struct airoha_gdm_dev { * QDMA migration. */ spinlock_t txq_lock[AIROHA_NUM_NETDEV_TX_RINGS]; + + struct phylink *phylink; + struct phylink_config phylink_config; }; struct airoha_gdm_port { @@ -619,6 +622,8 @@ struct airoha_gdm_port { /* protect concurrent hw_stats accesses */ spinlock_t stats_lock; + /* protect concurrent GDM4 register access */ + struct mutex link_lock; struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; }; diff --git a/drivers/net/ethernet/airoha/airoha_regs.h b/drivers/net/ethernet/airoha/airoha_regs.h index 07dd04859fde..94d53d4c3ab7 100644 --- a/drivers/net/ethernet/airoha/airoha_regs.h +++ b/drivers/net/ethernet/airoha/airoha_regs.h @@ -371,6 +371,18 @@ #define IP_FRAGMENT_PORT_MASK GENMASK(8, 5) #define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0) +#define REG_FE_GDM4_TMBI_FRAG 0x2028 +#define GDM4_SGMII1_TX_WEIGHT_MASK GENMASK(31, 26) +#define GDM4_SGMII1_TX_FRAG_SIZE_MASK GENMASK(25, 16) +#define GDM4_SGMII0_TX_WEIGHT_MASK GENMASK(15, 10) +#define GDM4_SGMII0_TX_FRAG_SIZE_MASK GENMASK(9, 0) + +#define REG_FE_GDM4_RMBI_FRAG 0x202c +#define GDM4_SGMII1_RX_WEIGHT_MASK GENMASK(31, 26) +#define GDM4_SGMII1_RX_FRAG_SIZE_MASK GENMASK(25, 16) +#define GDM4_SGMII0_RX_WEIGHT_MASK GENMASK(15, 10) +#define GDM4_SGMII0_RX_FRAG_SIZE_MASK GENMASK(9, 0) + #define REG_MC_VLAN_EN 0x2100 #define MC_VLAN_EN_MASK BIT(0) -- 2.55.0