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Mon, 05 Oct 2026 23:42:55 -0700 (PDT) Received: from localhost.localdomain ([2a09:bac5:55f5:25c3::3c3:b]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-35146a2c991sm4617347eec.14.2026.10.05.23.42.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2026 23:42:55 -0700 (PDT) From: Chuanhong Guo Date: Tue, 06 Oct 2026 14:42:23 +0800 Subject: [PATCH 1/2] dt-bindings: clock: mediatek: mt7629: add RTC clock IDs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261006-b4-mt7629-rtc-v1-1-e556386df816@gmail.com> References: <20261006-b4-mt7629-rtc-v1-0-e556386df816@gmail.com> In-Reply-To: <20261006-b4-mt7629-rtc-v1-0-e556386df816@gmail.com> To: AngeloGioacchino Del Regno , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chuanhong Guo X-Mailer: b4 0.14.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261005_234256_284956_99E61FE4 X-CRM114-Status: GOOD ( 11.28 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Expose the 40 MHz / 1221 RTC source and the RTC clock mux. Keep the existing CLK_TOP_RTC ID for the 40 MHz / 1024 source. Signed-off-by: Chuanhong Guo --- include/dt-bindings/clock/mt7629-clk.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/mt7629-clk.h b/include/dt-bindings/clock/mt7629-clk.h index ad8e6d7f0154..aa94a398ae05 100644 --- a/include/dt-bindings/clock/mt7629-clk.h +++ b/include/dt-bindings/clock/mt7629-clk.h @@ -115,7 +115,9 @@ #define CLK_TOP_CRYPTO_SEL 105 #define CLK_TOP_SGMII_REF_1_SEL 106 #define CLK_TOP_10M_SEL 107 -#define CLK_TOP_NR_CLK 108 +#define CLK_TOP_RTC_32K 108 +#define CLK_TOP_RTC_SEL 109 +#define CLK_TOP_NR_CLK 110 /* INFRACFG */ #define CLK_INFRA_MUX1_SEL 0 -- 2.55.0