From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE79F60A3802 for ; Tue, 10 Nov 2026 17:39:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=W9BcmAGZ DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Unsubscribe-Post:List-Owner; bh=0/ZUbsNW/rTrwtYCty/I8a6/S6q6DnVD6SqTQlAtUic=; b=W9BcmAGZO6FmQQ1Whyup5mSi3z jBWaCD6iYjckrmw1qXn4u0AyIukTvHUlUVyBaBAfGC+tvIVwST+D6zXSNvSVZp7LSmS/CrHoJmEhS p9h9OK1GSjMYTqM7FwdR4BIco/li5/Twd9zGh6eNurQFsp+9FRFLkRDZCc9zu5Y6nSDYGR3gODgUm 5Xy7TY4SRiSDT/+/vriK308aeh0HKPS91wy+qsSYexAeCDDhWdA0WPp5xeO4hn4Xd/8PTda8K8/Os 0OzIzsZ8EPTQtip1hj9kGIjhtxPk5zdscyIs/0J8eVNq9yEDb1lyuLBYFsvIYN5okSn0D6zpSMYMx 3R17vqFQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xQpp7-00000004hWS-2CQN; Tue, 10 Nov 2026 17:39:57 +0000 Received: from nbd.name ([46.4.11.11]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xQpp4-00000004hTj-0yql for linux-mediatek@lists.infradead.org; Tue, 10 Nov 2026 17:39:55 +0000 Received: from [2a04:4540:1403:9bfc:b113:5373:d0ec:2ad1] (helo=bertha10..) by ds12 with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1xQpox-001CWh-31; Tue, 10 Nov 2026 18:39:47 +0100 From: John Crispin To: Lorenzo Bianconi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski Cc: Ahmed Naseef , Benjamin Larsson , Christian Marangi , devicetree@vger.kernel.org, lei.dong@airoha.com, Linqi.zhang@airoha.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, mfd@lists.linux.dev, Mikhail Kshevetskiy , Rajeev.kumar@airoha.com, upstream@airoha.com, Weifeng.xu@airoha.com, zhengping.zhang@airoha.com Subject: [PATCH 0/7] pinctrl: airoha: add AN7589 support Date: Tue, 10 Nov 2026 18:39:34 +0100 Message-Id: <20261110173941.301478-1-john@phrozen.org> X-Mailer: git-send-email 2.34.1 X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_093954_289990_5C4B9F16 X-CRM114-Status: GOOD ( 10.20 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" X-Spam-Status: No, score=-11.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The Airoha AN7589 has a GPIO controller like the EN7581 one, with a third bank for 74 GPIOs in total. Its pin functions are selected differently: a separate IOMUX block holds a 4 bit mode field per pin, eight pins per register, and mode 0 makes any pin a GPIO. The first four patches prepare the shared driver and change nothing for the SoCs it serves today: 1. The GPIO register layout moves into the match data, so a SoC can describe more than 64 pins. 2. A function group can carry one IOMUX mode per pin. A SoC describes its IOMUX in the match data: the width of the mode field and, from patch 4, the mode that makes a pin a GPIO. 3. The chip SCU becomes optional, as the AN7589 needs none. 4. A pin requested by gpiolib is put into GPIO mode through the IOMUX, so no per pin gpio function is needed. Patch 5 adds the bindings for the pin controller and the GPIO system controller it sits under. Patch 6 moves the GPIO register offsets to the common header, so the AN7589 data can describe its own register table, with no functional change. Patch 7 adds the AN7589 pin data. The series applies to next-20261105 and has no dependencies. John Crispin (7): pinctrl: airoha: make gpio register layout per SoC pinctrl: airoha: add per pin mode field mux pinctrl: airoha: make the chip SCU optional pinctrl: airoha: mux a requested GPIO through the IOMUX dt-bindings: pinctrl: airoha: add AN7589 pinctrl: airoha: move the GPIO register offsets to the common header pinctrl: airoha: add support of an7589 SoC .../mfd/airoha,an7589-gpio-sysctl.yaml | 66 ++ .../devicetree/bindings/mfd/syscon.yaml | 1 + .../pinctrl/airoha,an7589-pinctrl.yaml | 533 +++++++++++++ MAINTAINERS | 3 + drivers/pinctrl/airoha/Kconfig | 11 + drivers/pinctrl/airoha/Makefile | 1 + drivers/pinctrl/airoha/airoha-common.h | 41 +- drivers/pinctrl/airoha/pinctrl-airoha.c | 119 ++- drivers/pinctrl/airoha/pinctrl-an7563.c | 1 + drivers/pinctrl/airoha/pinctrl-an7581.c | 1 + drivers/pinctrl/airoha/pinctrl-an7583.c | 1 + drivers/pinctrl/airoha/pinctrl-an7589.c | 721 ++++++++++++++++++ drivers/pinctrl/airoha/pinctrl-en7523.c | 1 + drivers/pinctrl/airoha/pinctrl-en7528.c | 1 + 14 files changed, 1469 insertions(+), 32 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an7589-gpio-sysctl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,an7589-pinctrl.yaml create mode 100644 drivers/pinctrl/airoha/pinctrl-an7589.c base-commit: ddfe51b0a0f5dc9e415cc2c8ad8db17532dd426b -- 2.34.1