From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Chen-Yu Tsai <wenst@chromium.org>, Laura Nao <laura.nao@collabora.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
p.zabel@pengutronix.de, richardcochran@gmail.com,
guangjie.song@mediatek.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
kernel@collabora.com
Subject: Re: [PATCH v5 14/27] clk: mediatek: Add MT8196 peripheral clock support
Date: Fri, 5 Sep 2025 10:11:52 +0200 [thread overview]
Message-ID: <2c681013-ca03-4f0f-8fe9-44475a97dfef@collabora.com> (raw)
In-Reply-To: <CAGXv+5Fj9Hwmk2y_bZhGX0EUEY42tm3t0nTrjtV-sYhD_B-xVg@mail.gmail.com>
Il 05/09/25 07:05, Chen-Yu Tsai ha scritto:
> On Fri, Aug 29, 2025 at 5:21 PM Laura Nao <laura.nao@collabora.com> wrote:
>>
>> Add support for the MT8196 peripheral clock controller, which provides
>> clock gate control for dma/flashif/msdc/pwm/spi/uart.
>>
>> Signed-off-by: Laura Nao <laura.nao@collabora.com>
>
> Not sure why CLK_OPS_PARENT_ENABLE was removed, but it does seem like the
> right thing to do, since this block is always on and doesn't require a
> clock to be enabled before accessing the registers.
>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> # CLK_OPS_PARENT_ENABLE change
>
> Note that I did not go through the bit definitions. I assume the other
> Collabora folks did a good job of reviewing those.
Yes, I did :-)
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cheers,
Angelo
next prev parent reply other threads:[~2025-09-05 9:26 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-29 9:18 [PATCH v5 00/27] Add support for MT8196 clock controllers Laura Nao
2025-08-29 9:18 ` [PATCH v5 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-08-29 9:18 ` [PATCH v5 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-08-29 9:18 ` [PATCH v5 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-09-05 4:09 ` Chen-Yu Tsai
2025-08-29 9:18 ` [PATCH v5 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-08-29 9:18 ` [PATCH v5 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-09-05 4:11 ` Chen-Yu Tsai
2025-08-29 9:18 ` [PATCH v5 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-09-05 4:13 ` Chen-Yu Tsai
2025-09-05 8:20 ` AngeloGioacchino Del Regno
2025-08-29 9:18 ` [PATCH v5 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-09-05 4:25 ` Chen-Yu Tsai
2025-08-29 9:18 ` [PATCH v5 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-08-29 9:18 ` [PATCH v5 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers Laura Nao
2025-08-29 9:18 ` [PATCH v5 10/27] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-08-29 9:18 ` [PATCH v5 11/27] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-08-29 9:18 ` [PATCH v5 12/27] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-08-29 9:18 ` [PATCH v5 13/27] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-09-05 5:01 ` Chen-Yu Tsai
2025-09-05 8:20 ` AngeloGioacchino Del Regno
2025-08-29 9:19 ` [PATCH v5 14/27] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-09-05 5:05 ` Chen-Yu Tsai
2025-09-05 8:11 ` AngeloGioacchino Del Regno [this message]
2025-08-29 9:19 ` [PATCH v5 15/27] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-09-05 6:36 ` Chen-Yu Tsai
2025-09-05 8:40 ` AngeloGioacchino Del Regno
2025-08-29 9:19 ` [PATCH v5 16/27] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-09-05 7:24 ` Chen-Yu Tsai
2025-08-29 9:19 ` [PATCH v5 17/27] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-08-29 9:19 ` [PATCH v5 18/27] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-08-29 9:19 ` [PATCH v5 19/27] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-09-05 8:04 ` Chen-Yu Tsai
2025-09-05 8:39 ` AngeloGioacchino Del Regno
2025-09-05 8:53 ` Chen-Yu Tsai
2025-09-15 10:33 ` AngeloGioacchino Del Regno
2025-08-29 9:19 ` [PATCH v5 20/27] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-08-29 9:19 ` [PATCH v5 21/27] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-08-29 9:19 ` [PATCH v5 22/27] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-09-05 8:03 ` Chen-Yu Tsai
2025-09-05 8:40 ` AngeloGioacchino Del Regno
2025-08-29 9:19 ` [PATCH v5 23/27] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2026-04-02 6:30 ` Jason-JH Lin (林睿祥)
2026-04-02 10:05 ` Laura Nao
2026-04-03 8:54 ` Jason-JH Lin (林睿祥)
[not found] ` <CAHCN7x+K25H-QWLDA6SoGSzxv9koO0wFOrjfWNePc+0AfjCVZg@mail.gmail.com>
2026-04-09 6:30 ` Jason-JH Lin (林睿祥)
2025-08-29 9:19 ` [PATCH v5 24/27] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-08-29 9:19 ` [PATCH v5 25/27] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-08-29 9:19 ` [PATCH v5 26/27] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-08-29 9:19 ` [PATCH v5 27/27] clk: mediatek: Add MT8196 vencsys " Laura Nao
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