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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Ahmed Naseef <naseefkm@gmail.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
	Caleb James DeLisle <cjd@cjdns.fr>,
	 linux-pci@vger.kernel.org, linux-mips@vger.kernel.org,
	 ryder.lee@mediatek.com, bhelgaas@google.com,
	lpieralisi@kernel.org,  kwilczynski@kernel.org, mani@kernel.org,
	robh@kernel.org,  krzk+dt@kernel.org, conor+dt@kernel.org,
	matthias.bgg@gmail.com,  angelogioacchino.delregno@collabora.com,
	ansuelsmth@gmail.com,  linux-mediatek@lists.infradead.org,
	devicetree@vger.kernel.org,  LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 3/3] PCI: Skip bridge window reads when window is not supported
Date: Wed, 18 Mar 2026 14:18:22 +0200 (EET)	[thread overview]
Message-ID: <2d47f78f-22cf-78c8-8312-3ffb095d2693@linux.intel.com> (raw)
In-Reply-To: <fc927b7f-a820-d3c2-581c-ab6db562bcfb@linux.intel.com>

[-- Attachment #1: Type: text/plain, Size: 3377 bytes --]

On Wed, 18 Mar 2026, Ilpo Järvinen wrote:

> On Wed, 18 Mar 2026, Ahmed Naseef wrote:
> 
> > On Tue, Mar 17, 2026 at 04:29:08PM -0500, Bjorn Helgaas wrote:
> > > On Mon, Mar 16, 2026 at 03:51:57PM +0000, Caleb James DeLisle wrote:
> > > > pci_read_bridge_io() and pci_read_bridge_mmio_pref() read bridge window
> > > > registers unconditionally. If the registers are hardwired to zero
> > > > (not implemented), both base and limit will be 0. Since (0 <= 0) is
> > > > true, a bogus window [mem 0x00000000-0x000fffff] or [io 0x0000-0x0fff]
> > > > gets created.
> > > > 
> > > > pci_read_bridge_windows() already detects unsupported windows by
> > > > testing register writability and sets io_window/pref_window flags
> > > > accordingly. Check these flags at the start of pci_read_bridge_io()
> > > > and pci_read_bridge_mmio_pref() to skip reading registers when the
> > > > window is not supported.
> > > 
> > > The fundamental problem here is that assigned space to a bridge window
> > > that isn't implemented.  I wish we understood the connection between
> > > this "read window" path and the assignment path.
> > > 
> > > Maybe this patch fixes it because we enter pci_read_bridge_mmio_pref()
> > > with res->flags being NULL, and we set IORESOURCE_MEM |
> > > IORESOURCE_PREFETCH again, which makes it look like we can assign
> > > space for it?
> > 
> > Yes, that's exactly right.
> > 
> > > 
> > > If that's the case, I think it would improve the commit log to mention
> > > the actual mechanism by which we avoid assigning space.
> > > 
> > 
> > How about this:
> > 
> >   pci_read_bridge_io() and pci_read_bridge_mmio_pref() read
> >   bridge window registers unconditionally. If the registers
> >   are hardwired to zero (not implemented), both base and limit
> >   will be 0. Since (0 <= 0) is true, these functions set
> >   IORESOURCE_IO or IORESOURCE_MEM | IORESOURCE_PREFETCH on
> >   the bridge resource. This causes the allocator to assign
> >   space for the window even though the hardware can't
> >   implement it.
> > 
> >   pci_read_bridge_windows() already detects unsupported windows
> >   by testing register writability and sets io_window/pref_window
> >   flags accordingly. Check these flags at the start of
> >   pci_read_bridge_io() and pci_read_bridge_mmio_pref() to skip
> >   reading registers when the window is not supported, so the
> >   resource flags remain clear and the allocator does not assign
> >   space for non-existent windows.
> 
> At least to me the proposed text reads much better than the original.
> The original text required reading between the lines to connect the dots, 
> whereas this new one clearly explains what causes what.

Hi again,

Reading the code I think the entire 0 <= 0 part is a red herring 
when it comes to the current code, the flags are always set by the 
functions!

The code would only add IORESOURCE_UNSET | IORESOURCE_DISABLED if the 
base <= limit check fails but that's still wrong because it says to the 
resource allocation code that it can enable that bridge window if it needs 
to.

Prior to the commit 8278c6914306 ("PCI: Preserve bridge window resource 
type flags") the base <= limit check did play some role (maybe the 
original commit message was based on some older tree than the most current 
one).

-- 
 i.

  reply	other threads:[~2026-03-18 12:18 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-16 15:51 [PATCH v2 0/3] PCI: mediatek: Add support for EcoNet SoCs Caleb James DeLisle
2026-03-16 15:51 ` [PATCH v2 1/3] dt-bindings: PCI: mediatek: Add support for EcoNet EN7528 Caleb James DeLisle
2026-03-17  7:26   ` Krzysztof Kozlowski
2026-03-18 20:42     ` Caleb James DeLisle
2026-03-16 15:51 ` [PATCH v2 2/3] PCI: mediatek: Add support for EcoNet EN7528 SoC Caleb James DeLisle
2026-03-16 15:51 ` [PATCH v2 3/3] PCI: Skip bridge window reads when window is not supported Caleb James DeLisle
2026-03-17 21:29   ` Bjorn Helgaas
2026-03-18  6:26     ` Ahmed Naseef
2026-03-18 12:04       ` Ilpo Järvinen
2026-03-18 12:18         ` Ilpo Järvinen [this message]
2026-03-18 13:12           ` Ahmed Naseef
2026-03-18 21:58   ` Bjorn Helgaas
2026-03-18 22:18     ` Caleb James DeLisle

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