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Wed, 2 Apr 2025 12:07:17 +0200 (CEST) Message-ID: <33847b76-11b5-4233-a5e6-9f8fd3c691a2@collabora.com> Date: Wed, 2 Apr 2025 12:07:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/2] arm64: dts: mediatek: mt8195: Add subsys clks for PCIe power domains To: Chen-Yu Tsai Cc: linux-mediatek@lists.infradead.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, weiyi.lu@mediatek.com, tinghan.shen@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com References: <20250402090615.25871-1-angelogioacchino.delregno@collabora.com> <20250402090615.25871-2-angelogioacchino.delregno@collabora.com> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250402_030719_929087_407F5926 X-CRM114-Status: GOOD ( 18.18 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Il 02/04/25 11:34, Chen-Yu Tsai ha scritto: > On Wed, Apr 2, 2025 at 5:10 PM AngeloGioacchino Del Regno > wrote: >> >> The PCIe MAC needs the sram to be powered on for internal IP >> access and it has always worked before because the bootloader >> on Chromebooks was leaving the PCIe PERI_AO MEM clocks on >> before booting the kernel. >> Add the SRAM (mem) clock as a subsystem clock on the PCIe MAC >> P0 and P1 to correctly describe the hardware and to avoid any >> issue with bootloaders behaving differently. >> >> Fixes: 2b515194bf0c ("arm64: dts: mt8195: Add power domains controller") >> Signed-off-by: AngeloGioacchino Del Regno >> --- >> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi >> index b33726da900b..0cb96cba727a 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi >> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi >> @@ -792,12 +792,16 @@ power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { >> >> power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { >> reg = ; >> + clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; >> + clock-names = "ss-pextp0-mem"; > > Doesn't the PCIe host controller already reference this clock? > >> mediatek,infracfg = <&infracfg_ao>; >> #power-domain-cells = <0>; >> }; >> >> power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { >> reg = ; >> + clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P1_MEM>; >> + clock-names = "ss-pextp1-mem"; > > Not this one though, since: > > /* Designer has connect pcie1 with peri_mem_p0 clock */ > <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; > I'm not sure what this comment refers to - as in, whether this is referring to the board designer or to the SoC//IP designer... ...but if MediaTek can clarify, I'd be happy :-) Cheers, Angelo > > ChenYu > >> mediatek,infracfg = <&infracfg_ao>; >> #power-domain-cells = <0>; >> }; >> -- >> 2.48.1 >> >>