[PATCH v1 0/7] ufs: host: mediatek: Provide features and fixes in MediaTek platforms

[PATCH v1 0/7] ufs: host: mediatek: Provide features and fixes in MediaTek platforms

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This series fixes some defects and provide features in MediaTek UFS drivers.

Peter Wang (3):
  ufs: host: mediatek: fix vsx/vccqx control logic
  ufs: host: mediatek: tx skew fix
  ufs: host: mediatek: support mphy reset

Po-Wen Kao  (3):
  ufs: host: mediatek: Add UFS_MTK_CAP_DISABLE_MCQ
  ufs: host: mediatek: ufs mtk sip command reconstruct
  ufs: host: mediatek: rename host power control API

Alice Chao (1):
  ufs: host: mediatek: support rtff in PM flow

 drivers/ufs/host/ufs-mediatek-sip.h |  94 ++++++++++++++++++++
 drivers/ufs/host/ufs-mediatek.c     | 130 ++++++++++++++++++++++++----
 drivers/ufs/host/ufs-mediatek.h     |  89 +++----------------
 3 files changed, 219 insertions(+), 94 deletions(-)
 create mode 100755 drivers/ufs/host/ufs-mediatek-sip.h

-- 
2.18.0

[PATCH v1 1/7] ufs: host: mediatek: fix vsx/vccqx control logic

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

VSX(the upper layer of VCCQ/VCCQ2) should
1. Always set to hpm mode if ufs device is active.
2. Enter lpm mode only if ufs device is not active.

VCCQX should
1. Keep hpm mode if vccq and vccq2 not set in dts.
2. Keep hpm mode if vcc not set in dts keep vcc always on.
3. Keep hpm if broken vcc keep vcc always on and not allow vccq lpm.
4. Except upper case, can enter lpm mode if ufs device is not active.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 41 +++++++++++++++++++++++----------
 drivers/ufs/host/ufs-mediatek.h |  5 ++++
 2 files changed, 34 insertions(+), 12 deletions(-)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 776bca4f70c8..6fc6fa2ea5bd 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -119,6 +119,13 @@ static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba)
 	return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);
 }
 
+static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
+{
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
+	return !!(host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);
+}
+
 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
 {
 	u32 tmp;
@@ -1271,27 +1278,37 @@ static void ufs_mtk_vsx_set_lpm(struct ufs_hba *hba, bool lpm)
 
 static void ufs_mtk_dev_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
 {
-	if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
-		return;
+	bool skip_vccqx = false;
 
-	/* Skip if VCC is assumed always-on */
-	if (!hba->vreg_info.vcc)
-		return;
-
-	/* Bypass LPM when device is still active */
+	/* Prevent entering LPM when device is still active */
 	if (lpm && ufshcd_is_ufs_dev_active(hba))
 		return;
 
-	/* Bypass LPM if VCC is enabled */
-	if (lpm && hba->vreg_info.vcc->enabled)
-		return;
+	/* Skip vccqx lpm control and control vsx only */
+	if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
+		skip_vccqx = true;
+
+	/* VCC is always-on, control vsx only */
+	if (!hba->vreg_info.vcc)
+		skip_vccqx = true;
+
+	/* Broken vcc keep vcc always on, most case control vsx only */
+	if (lpm && hba->vreg_info.vcc && hba->vreg_info.vcc->enabled) {
+		/* Some device vccqx/vsx can enter lpm */
+		if (ufs_mtk_is_allow_vccqx_lpm(hba))
+			skip_vccqx = false;
+		else /* control vsx only */
+			skip_vccqx = true;
+	}
 
 	if (lpm) {
-		ufs_mtk_vccqx_set_lpm(hba, lpm);
+		if (!skip_vccqx)
+			ufs_mtk_vccqx_set_lpm(hba, lpm);
 		ufs_mtk_vsx_set_lpm(hba, lpm);
 	} else {
 		ufs_mtk_vsx_set_lpm(hba, lpm);
-		ufs_mtk_vccqx_set_lpm(hba, lpm);
+		if (!skip_vccqx)
+			ufs_mtk_vccqx_set_lpm(hba, lpm);
 	}
 }
 
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index f76e80d91729..0720da2f1402 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -136,6 +136,11 @@ enum ufs_mtk_host_caps {
 	UFS_MTK_CAP_VA09_PWR_CTRL              = 1 << 1,
 	UFS_MTK_CAP_DISABLE_AH8                = 1 << 2,
 	UFS_MTK_CAP_BROKEN_VCC                 = 1 << 3,
+
+	/* Override UFS_MTK_CAP_BROKEN_VCC's behavior to
+	 * allow vccqx upstream to enter LPM
+	 */
+	UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
 	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
 };
 
-- 
2.18.0

[PATCH v1 2/7] ufs: host: mediatek: tx skew fix

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

Mediatek tx skew issue fix by check dts setting and vendor/model.
Then set PA_TACTIVATE set 8

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 21 +++++++++++++++++++++
 drivers/ufs/host/ufs-mediatek.h |  1 +
 2 files changed, 22 insertions(+)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 6fc6fa2ea5bd..0262e8994236 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -119,6 +119,13 @@ static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba)
 	return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);
 }
 
+static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba)
+{
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
+	return !!(host->caps & UFS_MTK_CAP_TX_SKEW_FIX);
+}
+
 static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -630,6 +637,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
 	if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto"))
 		host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO;
 
+	if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))
+		host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;
+
 	dev_info(hba->dev, "caps: 0x%x", host->caps);
 }
 
@@ -1423,6 +1433,17 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
 	if (mid == UFS_VENDOR_SAMSUNG) {
 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10);
+	} else if (mid == UFS_VENDOR_MICRON) {
+		/* Only for the host which have TX skew issue */
+		if (ufs_mtk_is_tx_skew_fix(hba) &&
+			(STR_PRFX_EQUAL("MT128GBCAV2U31", dev_info->model) ||
+			STR_PRFX_EQUAL("MT256GBCAV4U31", dev_info->model) ||
+			STR_PRFX_EQUAL("MT512GBCAV8U31", dev_info->model) ||
+			STR_PRFX_EQUAL("MT256GBEAX4U40", dev_info->model) ||
+			STR_PRFX_EQUAL("MT512GAYAX4U40", dev_info->model) ||
+			STR_PRFX_EQUAL("MT001TAYAX8U40", dev_info->model))) {
+			ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8);
+		}
 	}
 
 	/*
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 0720da2f1402..146c25080599 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -142,6 +142,7 @@ enum ufs_mtk_host_caps {
 	 */
 	UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
 	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
+	UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
 };
 
 struct ufs_mtk_crypt_cfg {
-- 
2.18.0

[PATCH v1 3/7] ufs: host: mediatek: Add UFS_MTK_CAP_DISABLE_MCQ

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

From: Po-Wen Kao <powen.kao@mediatek.com>

Add new mediatek host cap UFS_MTK_CAP_DISABLE_MCQ to allow disable
MCQ feature by assigning dts boolean property
"mediatek,ufs-disable-mcq""

Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Po-Wen Kao <powen.kao@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 12 ++++++++++++
 drivers/ufs/host/ufs-mediatek.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 0262e8994236..cdf29cfa490b 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -640,6 +640,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
 	if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))
 		host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;
 
+	if (of_property_read_bool(np, "mediatek,ufs-disable-mcq"))
+		host->caps |= UFS_MTK_CAP_DISABLE_MCQ;
+
 	dev_info(hba->dev, "caps: 0x%x", host->caps);
 }
 
@@ -874,6 +877,9 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba)
 	host->mcq_nr_intr = UFSHCD_MAX_Q_NR;
 	pdev = container_of(hba->dev, struct platform_device, dev);
 
+	if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
+		goto failed;
+
 	for (i = 0; i < host->mcq_nr_intr; i++) {
 		/* irq index 0 is legacy irq, sq/cq irq start from index 1 */
 		irq = platform_get_irq(pdev, i + 1);
@@ -1585,6 +1591,12 @@ static int ufs_mtk_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
 
 static int ufs_mtk_get_hba_mac(struct ufs_hba *hba)
 {
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
+	/* MCQ operation not permitted */
+	if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
+		return -EPERM;
+
 	return MAX_SUPP_MAC;
 }
 
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 146c25080599..79c64de25254 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -143,6 +143,7 @@ enum ufs_mtk_host_caps {
 	UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
 	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
 	UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
+	UFS_MTK_CAP_DISABLE_MCQ                = 1 << 8,
 };
 
 struct ufs_mtk_crypt_cfg {
-- 
2.18.0

[PATCH v1 4/7] ufs: host: mediatek: ufs mtk sip command reconstruct

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

From: Po-Wen Kao <powen.kao@mediatek.com>

Move sip command and define to a new sip header file.

Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Po-Wen Kao <powen.kao@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek-sip.h | 90 +++++++++++++++++++++++++++++
 drivers/ufs/host/ufs-mediatek.c     |  3 +-
 drivers/ufs/host/ufs-mediatek.h     | 79 -------------------------
 3 files changed, 92 insertions(+), 80 deletions(-)
 create mode 100755 drivers/ufs/host/ufs-mediatek-sip.h

diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-mediatek-sip.h
new file mode 100755
index 000000000000..30146bb1ccbe
--- /dev/null
+++ b/drivers/ufs/host/ufs-mediatek-sip.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+
+#ifndef _UFS_MEDIATEK_SIP_H
+#define _UFS_MEDIATEK_SIP_H
+
+#include <linux/soc/mediatek/mtk_sip_svc.h>
+
+/*
+ * SiP commands
+ */
+#define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)
+#define UFS_MTK_SIP_VA09_PWR_CTRL         BIT(0)
+#define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
+#define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
+#define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
+#define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)
+#define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
+#define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
+
+
+/*
+ * Multi-VCC by Numbering
+ */
+enum ufs_mtk_vcc_num {
+	UFS_VCC_NONE = 0,
+	UFS_VCC_1,
+	UFS_VCC_2,
+	UFS_VCC_MAX
+};
+
+/*
+ * Host Power Control options
+ */
+enum {
+	HOST_PWR_HCI = 0,
+	HOST_PWR_MPHY
+};
+
+/*
+ * SMC call wrapper function
+ */
+struct ufs_mtk_smc_arg {
+	unsigned long cmd;
+	struct arm_smccc_res *res;
+	unsigned long v1;
+	unsigned long v2;
+	unsigned long v3;
+	unsigned long v4;
+	unsigned long v5;
+	unsigned long v6;
+	unsigned long v7;
+};
+
+
+static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
+{
+	arm_smccc_smc(MTK_SIP_UFS_CONTROL,
+		s.cmd,
+		s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);
+}
+
+#define ufs_mtk_smc(...) \
+	_ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})
+
+/* Sip kernel interface */
+#define ufs_mtk_va09_pwr_ctrl(res, on) \
+	ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)
+
+#define ufs_mtk_crypto_ctrl(res, enable) \
+	ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)
+
+#define ufs_mtk_ref_clk_notify(on, stage, res) \
+	ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage)
+
+#define ufs_mtk_device_reset_ctrl(high, res) \
+	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
+
+#define ufs_mtk_host_pwr_ctrl(opt, on, res) \
+	ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
+
+#define ufs_mtk_get_vcc_num(res) \
+	ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
+
+#define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \
+	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version)
+
+#endif /* !_UFS_MEDIATEK_SIP_H */
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index cdf29cfa490b..ae184e4f90e6 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -20,13 +20,14 @@
 #include <linux/pm_qos.h>
 #include <linux/regulator/consumer.h>
 #include <linux/reset.h>
-#include <linux/soc/mediatek/mtk_sip_svc.h>
 
 #include <ufs/ufshcd.h>
 #include "ufshcd-pltfrm.h"
 #include <ufs/ufs_quirks.h>
 #include <ufs/unipro.h>
+
 #include "ufs-mediatek.h"
+#include "ufs-mediatek-sip.h"
 
 static int  ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq);
 
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 79c64de25254..17be3f748fa0 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -8,7 +8,6 @@
 
 #include <linux/bitops.h>
 #include <linux/pm_qos.h>
-#include <linux/soc/mediatek/mtk_sip_svc.h>
 
 /*
  * MCQ define and struct
@@ -100,18 +99,6 @@ enum {
 	VS_HIB_EXIT                 = 13,
 };
 
-/*
- * SiP commands
- */
-#define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)
-#define UFS_MTK_SIP_VA09_PWR_CTRL         BIT(0)
-#define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
-#define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
-#define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
-#define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)
-#define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
-#define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
-
 /*
  * VS_DEBUGCLOCKENABLE
  */
@@ -197,70 +184,4 @@ struct ufs_mtk_host {
 	struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
 };
 
-/*
- * Multi-VCC by Numbering
- */
-enum ufs_mtk_vcc_num {
-	UFS_VCC_NONE = 0,
-	UFS_VCC_1,
-	UFS_VCC_2,
-	UFS_VCC_MAX
-};
-
-/*
- * Host Power Control options
- */
-enum {
-	HOST_PWR_HCI = 0,
-	HOST_PWR_MPHY
-};
-
-/*
- * SMC call wrapper function
- */
-struct ufs_mtk_smc_arg {
-	unsigned long cmd;
-	struct arm_smccc_res *res;
-	unsigned long v1;
-	unsigned long v2;
-	unsigned long v3;
-	unsigned long v4;
-	unsigned long v5;
-	unsigned long v6;
-	unsigned long v7;
-};
-
-static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
-{
-	arm_smccc_smc(MTK_SIP_UFS_CONTROL,
-		      s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);
-}
-
-#define ufs_mtk_smc(...) \
-	_ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})
-
-/*
- * SMC call interface
- */
-#define ufs_mtk_va09_pwr_ctrl(res, on) \
-	ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)
-
-#define ufs_mtk_crypto_ctrl(res, enable) \
-	ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)
-
-#define ufs_mtk_ref_clk_notify(on, stage, res) \
-	ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage)
-
-#define ufs_mtk_device_reset_ctrl(high, res) \
-	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
-
-#define ufs_mtk_host_pwr_ctrl(opt, on, res) \
-	ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
-
-#define ufs_mtk_get_vcc_num(res) \
-	ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
-
-#define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \
-	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver)
-
 #endif /* !_UFS_MEDIATEK_H */
-- 
2.18.0

[PATCH v1 5/7] ufs: host: mediatek: rename host power control API

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

From: Po-Wen Kao <powen.kao@mediatek.com>

Host power control is control crypto sram power.
Rename it for easy maintain.

Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Po-Wen Kao <powen.kao@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek-sip.h | 13 +++----------
 drivers/ufs/host/ufs-mediatek.c     |  4 ++--
 2 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-mediatek-sip.h
index 30146bb1ccbe..fd640846910a 100755
--- a/drivers/ufs/host/ufs-mediatek-sip.h
+++ b/drivers/ufs/host/ufs-mediatek-sip.h
@@ -16,7 +16,7 @@
 #define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
 #define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
-#define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)
+#define UFS_MTK_SIP_SRAM_PWR_CTRL         BIT(5)
 #define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
 #define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
 
@@ -31,13 +31,6 @@ enum ufs_mtk_vcc_num {
 	UFS_VCC_MAX
 };
 
-/*
- * Host Power Control options
- */
-enum {
-	HOST_PWR_HCI = 0,
-	HOST_PWR_MPHY
-};
 
 /*
  * SMC call wrapper function
@@ -78,8 +71,8 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
 #define ufs_mtk_device_reset_ctrl(high, res) \
 	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
 
-#define ufs_mtk_host_pwr_ctrl(opt, on, res) \
-	ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
+#define ufs_mtk_sram_pwr_ctrl(on, res) \
+	ufs_mtk_smc(UFS_MTK_SIP_SRAM_PWR_CTRL, &(res), on)
 
 #define ufs_mtk_get_vcc_num(res) \
 	ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index ae184e4f90e6..2caf0c1d4e17 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1376,7 +1376,7 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
 	if (ufshcd_is_link_off(hba))
 		ufs_mtk_device_reset_ctrl(0, res);
 
-	ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, false, res);
+	ufs_mtk_sram_pwr_ctrl(false, res);
 
 	return 0;
 fail:
@@ -1397,7 +1397,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 	if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
 		ufs_mtk_dev_vreg_set_lpm(hba, false);
 
-	ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, true, res);
+	ufs_mtk_sram_pwr_ctrl(true, res);
 
 	err = ufs_mtk_mphy_power_on(hba, true);
 	if (err)
-- 
2.18.0

[PATCH v1 6/7] ufs: host: mediatek: support mphy reset

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This patch will reset mphy when host reset.
Backup mphy setting after mphy reset control get.
Restore mphy setting after mphy reset.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek-sip.h |  9 ++++++++-
 drivers/ufs/host/ufs-mediatek.c     | 14 ++++++++++++++
 drivers/ufs/host/ufs-mediatek.h     |  1 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-mediatek-sip.h
index fd640846910a..64f48ecc54c7 100755
--- a/drivers/ufs/host/ufs-mediatek-sip.h
+++ b/drivers/ufs/host/ufs-mediatek-sip.h
@@ -19,7 +19,7 @@
 #define UFS_MTK_SIP_SRAM_PWR_CTRL         BIT(5)
 #define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
 #define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
-
+#define UFS_MTK_SIP_MPHY_CTRL             BIT(8)
 
 /*
  * Multi-VCC by Numbering
@@ -31,6 +31,10 @@ enum ufs_mtk_vcc_num {
 	UFS_VCC_MAX
 };
 
+enum ufs_mtk_mphy_op {
+	UFS_MPHY_BACKUP = 0,
+	UFS_MPHY_RESTORE
+};
 
 /*
  * SMC call wrapper function
@@ -80,4 +84,7 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
 #define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \
 	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version)
 
+#define ufs_mtk_mphy_ctrl(op, res) \
+	ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op)
+
 #endif /* !_UFS_MEDIATEK_SIP_H */
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 2caf0c1d4e17..c4aae031b694 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -185,16 +185,23 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
 static void ufs_mtk_host_reset(struct ufs_hba *hba)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+	struct arm_smccc_res res;
 
 	reset_control_assert(host->hci_reset);
 	reset_control_assert(host->crypto_reset);
 	reset_control_assert(host->unipro_reset);
+	reset_control_assert(host->mphy_reset);
 
 	usleep_range(100, 110);
 
 	reset_control_deassert(host->unipro_reset);
 	reset_control_deassert(host->crypto_reset);
 	reset_control_deassert(host->hci_reset);
+	reset_control_deassert(host->mphy_reset);
+
+	/* restore mphy setting aftre mphy reset */
+	if (host->mphy_reset)
+		ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res);
 }
 
 static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
@@ -219,6 +226,8 @@ static void ufs_mtk_init_reset(struct ufs_hba *hba)
 				   "unipro_rst");
 	ufs_mtk_init_reset_control(hba, &host->crypto_reset,
 				   "crypto_rst");
+	ufs_mtk_init_reset_control(hba, &host->mphy_reset,
+				   "mphy_rst");
 }
 
 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
@@ -918,6 +927,7 @@ static int ufs_mtk_init(struct ufs_hba *hba)
 	struct device *dev = hba->dev;
 	struct ufs_mtk_host *host;
 	int err = 0;
+	struct arm_smccc_res res;
 
 	host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
 	if (!host) {
@@ -946,6 +956,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
 
 	ufs_mtk_init_reset(hba);
 
+	/* backup mphy setting if mphy can reset */
+	if (host->mphy_reset)
+		ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res);
+
 	/* Enable runtime autosuspend */
 	hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
 
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 17be3f748fa0..6129ab59e5f5 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -166,6 +166,7 @@ struct ufs_mtk_host {
 	struct reset_control *hci_reset;
 	struct reset_control *unipro_reset;
 	struct reset_control *crypto_reset;
+	struct reset_control *mphy_reset;
 	struct ufs_hba *hba;
 	struct ufs_mtk_crypt_cfg *crypt;
 	struct ufs_mtk_clk mclk;
-- 
2.18.0

[PATCH v1 7/7] ufs: host: mediatek: support rtff in PM flow

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

From: Alice Chao <alice.chao@mediatek.com>

Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Alice Chao <alice.chao@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek-sip.h |  4 ++++
 drivers/ufs/host/ufs-mediatek.c     | 35 +++++++++++++++++++++++++++++
 drivers/ufs/host/ufs-mediatek.h     |  2 ++
 3 files changed, 41 insertions(+)

diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-mediatek-sip.h
index 64f48ecc54c7..eeab0f93146e 100755
--- a/drivers/ufs/host/ufs-mediatek-sip.h
+++ b/drivers/ufs/host/ufs-mediatek-sip.h
@@ -20,6 +20,7 @@
 #define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
 #define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
 #define UFS_MTK_SIP_MPHY_CTRL             BIT(8)
+#define UFS_MTK_SIP_MTCMOS_CTRL           BIT(9)
 
 /*
  * Multi-VCC by Numbering
@@ -87,4 +88,7 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
 #define ufs_mtk_mphy_ctrl(op, res) \
 	ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op)
 
+#define ufs_mtk_mtcmos_ctrl(op, res) \
+	ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op)
+
 #endif /* !_UFS_MEDIATEK_SIP_H */
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index c4aae031b694..2f191525c308 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -127,6 +127,13 @@ static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba)
 	return !!(host->caps & UFS_MTK_CAP_TX_SKEW_FIX);
 }
 
+static bool ufs_mtk_is_rtff_mtcmos(struct ufs_hba *hba)
+{
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
+	return !!(host->caps & UFS_MTK_CAP_RTFF_MTCMOS);
+}
+
 static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -653,6 +660,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
 	if (of_property_read_bool(np, "mediatek,ufs-disable-mcq"))
 		host->caps |= UFS_MTK_CAP_DISABLE_MCQ;
 
+	if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos"))
+		host->caps |= UFS_MTK_CAP_RTFF_MTCMOS;
+
 	dev_info(hba->dev, "caps: 0x%x", host->caps);
 }
 
@@ -993,6 +1003,15 @@ static int ufs_mtk_init(struct ufs_hba *hba)
 	 * Enable phy clocks specifically here.
 	 */
 	ufs_mtk_mphy_power_on(hba, true);
+
+	if (ufs_mtk_is_rtff_mtcmos(hba)) {
+		/* First Restore here, to avoid backup unexpected value */
+		ufs_mtk_mtcmos_ctrl(false, res);
+
+		/* Power on to init */
+		ufs_mtk_mtcmos_ctrl(true, res);
+	}
+
 	ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
 
 	host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
@@ -1823,6 +1842,7 @@ static void ufs_mtk_remove(struct platform_device *pdev)
 static int ufs_mtk_system_suspend(struct device *dev)
 {
 	struct ufs_hba *hba = dev_get_drvdata(dev);
+	struct arm_smccc_res res;
 	int ret;
 
 	ret = ufshcd_system_suspend(dev);
@@ -1831,15 +1851,22 @@ static int ufs_mtk_system_suspend(struct device *dev)
 
 	ufs_mtk_dev_vreg_set_lpm(hba, true);
 
+	if (ufs_mtk_is_rtff_mtcmos(hba))
+		ufs_mtk_mtcmos_ctrl(false, res);
+
 	return 0;
 }
 
 static int ufs_mtk_system_resume(struct device *dev)
 {
 	struct ufs_hba *hba = dev_get_drvdata(dev);
+	struct arm_smccc_res res;
 
 	ufs_mtk_dev_vreg_set_lpm(hba, false);
 
+	if (ufs_mtk_is_rtff_mtcmos(hba))
+		ufs_mtk_mtcmos_ctrl(true, res);
+
 	return ufshcd_system_resume(dev);
 }
 #endif
@@ -1848,6 +1875,7 @@ static int ufs_mtk_system_resume(struct device *dev)
 static int ufs_mtk_runtime_suspend(struct device *dev)
 {
 	struct ufs_hba *hba = dev_get_drvdata(dev);
+	struct arm_smccc_res res;
 	int ret = 0;
 
 	ret = ufshcd_runtime_suspend(dev);
@@ -1856,12 +1884,19 @@ static int ufs_mtk_runtime_suspend(struct device *dev)
 
 	ufs_mtk_dev_vreg_set_lpm(hba, true);
 
+	if (ufs_mtk_is_rtff_mtcmos(hba))
+		ufs_mtk_mtcmos_ctrl(false, res);
+
 	return 0;
 }
 
 static int ufs_mtk_runtime_resume(struct device *dev)
 {
 	struct ufs_hba *hba = dev_get_drvdata(dev);
+	struct arm_smccc_res res;
+
+	if (ufs_mtk_is_rtff_mtcmos(hba))
+		ufs_mtk_mtcmos_ctrl(true, res);
 
 	ufs_mtk_dev_vreg_set_lpm(hba, false);
 
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 6129ab59e5f5..599fea66663b 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -131,6 +131,8 @@ enum ufs_mtk_host_caps {
 	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
 	UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
 	UFS_MTK_CAP_DISABLE_MCQ                = 1 << 8,
+	/* Control MTCMOS with RTFF */
+	UFS_MTK_CAP_RTFF_MTCMOS                = 1 << 9,
 };
 
 struct ufs_mtk_crypt_cfg {
-- 
2.18.0

RE: [PATCH v1 2/7] ufs: host: mediatek: tx skew fix

[Avri Altman]

 
> From: Peter Wang <peter.wang@mediatek.com>
> 
> Mediatek tx skew issue fix by check dts setting and vendor/model.
> Then set PA_TACTIVATE set 8
> 
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> ---
>  drivers/ufs/host/ufs-mediatek.c | 21 +++++++++++++++++++++
> drivers/ufs/host/ufs-mediatek.h |  1 +
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
> index 6fc6fa2ea5bd..0262e8994236 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -119,6 +119,13 @@ static bool ufs_mtk_is_pmc_via_fastauto(struct
> ufs_hba *hba)
>         return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);  }
> 
> +static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba) {
> +       struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +
> +       return !!(host->caps & UFS_MTK_CAP_TX_SKEW_FIX); }
> +
>  static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)  {
>         struct ufs_mtk_host *host = ufshcd_get_variant(hba); @@ -630,6 +637,9
> @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
>         if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto"))
>                 host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO;
> 
> +       if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))
> +               host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;
> +
>         dev_info(hba->dev, "caps: 0x%x", host->caps);  }
> 
> @@ -1423,6 +1433,17 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba
> *hba)
>         if (mid == UFS_VENDOR_SAMSUNG) {
>                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
>                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10);
> +       } else if (mid == UFS_VENDOR_MICRON) {
Is this a quirk for micron? Why not implemented as a quirk?
And go for all this trouble setting it in the dt etc.

Thanks,
Avri

> +               /* Only for the host which have TX skew issue */
> +               if (ufs_mtk_is_tx_skew_fix(hba) &&
> +                       (STR_PRFX_EQUAL("MT128GBCAV2U31", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT256GBCAV4U31", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT512GBCAV8U31", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT256GBEAX4U40", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT512GAYAX4U40", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT001TAYAX8U40", dev_info->model))) {
> +                       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8);
> +               }
>         }
> 
>         /*
> diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
> index 0720da2f1402..146c25080599 100644
> --- a/drivers/ufs/host/ufs-mediatek.h
> +++ b/drivers/ufs/host/ufs-mediatek.h
> @@ -142,6 +142,7 @@ enum ufs_mtk_host_caps {
>          */
>         UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
>         UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
> +       UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
>  };
> 
>  struct ufs_mtk_crypt_cfg {
> --
> 2.18.0

RE: [PATCH v1 3/7] ufs: host: mediatek: Add UFS_MTK_CAP_DISABLE_MCQ

[Avri Altman]

> From: Peter Wang <peter.wang@mediatek.com>
> 
> From: Po-Wen Kao <powen.kao@mediatek.com>
> 
> Add new mediatek host cap UFS_MTK_CAP_DISABLE_MCQ to allow disable
> MCQ feature by assigning dts boolean property "mediatek,ufs-disable-mcq""
> 
> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Po-Wen Kao <powen.kao@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>


> ---
>  drivers/ufs/host/ufs-mediatek.c | 12 ++++++++++++  drivers/ufs/host/ufs-
> mediatek.h |  1 +
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
> index 0262e8994236..cdf29cfa490b 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -640,6 +640,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
>         if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))
>                 host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;
> 
> +       if (of_property_read_bool(np, "mediatek,ufs-disable-mcq"))
> +               host->caps |= UFS_MTK_CAP_DISABLE_MCQ;
> +
>         dev_info(hba->dev, "caps: 0x%x", host->caps);  }
> 
> @@ -874,6 +877,9 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba)
>         host->mcq_nr_intr = UFSHCD_MAX_Q_NR;
>         pdev = container_of(hba->dev, struct platform_device, dev);
> 
> +       if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
> +               goto failed;
> +
>         for (i = 0; i < host->mcq_nr_intr; i++) {
>                 /* irq index 0 is legacy irq, sq/cq irq start from index 1 */
>                 irq = platform_get_irq(pdev, i + 1); @@ -1585,6 +1591,12 @@ static
> int ufs_mtk_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
> 
>  static int ufs_mtk_get_hba_mac(struct ufs_hba *hba)  {
> +       struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +
> +       /* MCQ operation not permitted */
> +       if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
> +               return -EPERM;
> +
>         return MAX_SUPP_MAC;
>  }
> 
> diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
> index 146c25080599..79c64de25254 100644
> --- a/drivers/ufs/host/ufs-mediatek.h
> +++ b/drivers/ufs/host/ufs-mediatek.h
> @@ -143,6 +143,7 @@ enum ufs_mtk_host_caps {
>         UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
>         UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
>         UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
> +       UFS_MTK_CAP_DISABLE_MCQ                = 1 << 8,
>  };
> 
>  struct ufs_mtk_crypt_cfg {
> --
> 2.18.0

Re: [PATCH v1 2/7] ufs: host: mediatek: tx skew fix

[Peter Wang (王信友)]

On Fri, 2024-03-08 at 08:41 +0000, Avri Altman wrote:
> 
> Is this a quirk for micron? Why not implemented as a quirk?
> And go for all this trouble setting it in the dt etc.
> 
> Thanks,
> Avri
> 

Hi Arvi,

It is not for micron only. May have another device need this patch.
But corrently we only find micron divcie need host change TACTIVATE
value. And it is depend on host design, so we use dts to check if host
need this patch for dedicated ufs device.


Thanks.
Peter

RE: [PATCH v1 2/7] ufs: host: mediatek: tx skew fix

[Avri Altman]

> From: Peter Wang <peter.wang@mediatek.com>
> 
> Mediatek tx skew issue fix by check dts setting and vendor/model.
> Then set PA_TACTIVATE set 8
> 
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>


> ---
>  drivers/ufs/host/ufs-mediatek.c | 21 +++++++++++++++++++++
> drivers/ufs/host/ufs-mediatek.h |  1 +
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
> index 6fc6fa2ea5bd..0262e8994236 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -119,6 +119,13 @@ static bool ufs_mtk_is_pmc_via_fastauto(struct
> ufs_hba *hba)
>         return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);  }
> 
> +static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba) {
> +       struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +
> +       return !!(host->caps & UFS_MTK_CAP_TX_SKEW_FIX); }
> +
>  static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)  {
>         struct ufs_mtk_host *host = ufshcd_get_variant(hba); @@ -630,6 +637,9
> @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
>         if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto"))
>                 host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO;
> 
> +       if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))
> +               host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;
> +
>         dev_info(hba->dev, "caps: 0x%x", host->caps);  }
> 
> @@ -1423,6 +1433,17 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba
> *hba)
>         if (mid == UFS_VENDOR_SAMSUNG) {
>                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
>                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10);
> +       } else if (mid == UFS_VENDOR_MICRON) {
> +               /* Only for the host which have TX skew issue */
> +               if (ufs_mtk_is_tx_skew_fix(hba) &&
> +                       (STR_PRFX_EQUAL("MT128GBCAV2U31", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT256GBCAV4U31", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT512GBCAV8U31", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT256GBEAX4U40", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT512GAYAX4U40", dev_info->model) ||
> +                       STR_PRFX_EQUAL("MT001TAYAX8U40", dev_info->model))) {
> +                       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8);
> +               }
>         }
> 
>         /*
> diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
> index 0720da2f1402..146c25080599 100644
> --- a/drivers/ufs/host/ufs-mediatek.h
> +++ b/drivers/ufs/host/ufs-mediatek.h
> @@ -142,6 +142,7 @@ enum ufs_mtk_host_caps {
>          */
>         UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
>         UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
> +       UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
>  };
> 
>  struct ufs_mtk_crypt_cfg {
> --
> 2.18.0

RE: [PATCH v1 5/7] ufs: host: mediatek: rename host power control API

[Avri Altman]

> From: Peter Wang <peter.wang@mediatek.com>
> 
> From: Po-Wen Kao <powen.kao@mediatek.com>
> 
> Host power control is control crypto sram power.
> Rename it for easy maintain.
> 
> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Po-Wen Kao <powen.kao@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>


> ---
>  drivers/ufs/host/ufs-mediatek-sip.h | 13 +++----------
>  drivers/ufs/host/ufs-mediatek.c     |  4 ++--
>  2 files changed, 5 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-mediatek-
> sip.h
> index 30146bb1ccbe..fd640846910a 100755
> --- a/drivers/ufs/host/ufs-mediatek-sip.h
> +++ b/drivers/ufs/host/ufs-mediatek-sip.h
> @@ -16,7 +16,7 @@
>  #define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
>  #define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
>  #define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
> -#define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)
> +#define UFS_MTK_SIP_SRAM_PWR_CTRL         BIT(5)
>  #define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
>  #define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
> 
> @@ -31,13 +31,6 @@ enum ufs_mtk_vcc_num {
>         UFS_VCC_MAX
>  };
> 
> -/*
> - * Host Power Control options
> - */
> -enum {
> -       HOST_PWR_HCI = 0,
> -       HOST_PWR_MPHY
> -};
> 
>  /*
>   * SMC call wrapper function
> @@ -78,8 +71,8 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg
> s)  #define ufs_mtk_device_reset_ctrl(high, res) \
>         ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
> 
> -#define ufs_mtk_host_pwr_ctrl(opt, on, res) \
> -       ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
> +#define ufs_mtk_sram_pwr_ctrl(on, res) \
> +       ufs_mtk_smc(UFS_MTK_SIP_SRAM_PWR_CTRL, &(res), on)
> 
>  #define ufs_mtk_get_vcc_num(res) \
>         ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res)) diff --git
> a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index
> ae184e4f90e6..2caf0c1d4e17 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -1376,7 +1376,7 @@ static int ufs_mtk_suspend(struct ufs_hba *hba,
> enum ufs_pm_op pm_op,
>         if (ufshcd_is_link_off(hba))
>                 ufs_mtk_device_reset_ctrl(0, res);
> 
> -       ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, false, res);
> +       ufs_mtk_sram_pwr_ctrl(false, res);
> 
>         return 0;
>  fail:
> @@ -1397,7 +1397,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum
> ufs_pm_op pm_op)
>         if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
>                 ufs_mtk_dev_vreg_set_lpm(hba, false);
> 
> -       ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, true, res);
> +       ufs_mtk_sram_pwr_ctrl(true, res);
> 
>         err = ufs_mtk_mphy_power_on(hba, true);
>         if (err)
> --
> 2.18.0

Re: [PATCH v1 0/7] ufs: host: mediatek: Provide features and fixes in MediaTek platforms

[Chun-Hung Wu (巫駿宏)]

On Fri, 2024-03-08 at 15:02 +0800, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> This series fixes some defects and provide features in MediaTek UFS
> drivers.
> 
> Peter Wang (3):
>   ufs: host: mediatek: fix vsx/vccqx control logic
>   ufs: host: mediatek: tx skew fix
>   ufs: host: mediatek: support mphy reset
> 
> Po-Wen Kao  (3):
>   ufs: host: mediatek: Add UFS_MTK_CAP_DISABLE_MCQ
>   ufs: host: mediatek: ufs mtk sip command reconstruct
>   ufs: host: mediatek: rename host power control API
> 
> Alice Chao (1):
>   ufs: host: mediatek: support rtff in PM flow
> 
>  drivers/ufs/host/ufs-mediatek-sip.h |  94 ++++++++++++++++++++
>  drivers/ufs/host/ufs-mediatek.c     | 130 ++++++++++++++++++++++++
> ----
>  drivers/ufs/host/ufs-mediatek.h     |  89 +++----------------
>  3 files changed, 219 insertions(+), 94 deletions(-)
>  create mode 100755 drivers/ufs/host/ufs-mediatek-sip.h
> 
Acked-by: Chun-Hung Wu <chun-hung.wu@mediatek.com>

Re: [PATCH v1 1/7] ufs: host: mediatek: fix vsx/vccqx control logic

[Bart Van Assche]

On 3/7/24 23:02, peter.wang@mediatek.com wrote:
> +static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
> +{
> +	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +
> +	return !!(host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);
> +}

Please leave out the !!. The compiler does this for you when implicitly 
converting an int into a bool.

Thanks,

Bart.

Re: [PATCH v1 1/7] ufs: host: mediatek: fix vsx/vccqx control logic

[Chun-Hung Wu (巫駿宏)]

On Fri, 2024-03-08 at 15:02 +0800, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> VSX(the upper layer of VCCQ/VCCQ2) should
> 1. Always set to hpm mode if ufs device is active.
> 2. Enter lpm mode only if ufs device is not active.
> 
> VCCQX should
> 1. Keep hpm mode if vccq and vccq2 not set in dts.
> 2. Keep hpm mode if vcc not set in dts keep vcc always on.
> 3. Keep hpm if broken vcc keep vcc always on and not allow vccq lpm.
> 4. Except upper case, can enter lpm mode if ufs device is not active.
> 
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> ---
>  drivers/ufs/host/ufs-mediatek.c | 41 +++++++++++++++++++++++------
> ----
>  drivers/ufs/host/ufs-mediatek.h |  5 ++++
>  2 files changed, 34 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-
> mediatek.c
> index 776bca4f70c8..6fc6fa2ea5bd 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -119,6 +119,13 @@ static bool ufs_mtk_is_pmc_via_fastauto(struct
> ufs_hba *hba)
>  	return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);
>  }
>  
> +static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
> +{
> +	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +
> +	return !!(host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);
> +}
> +
>  static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
>  {
>  	u32 tmp;
> @@ -1271,27 +1278,37 @@ static void ufs_mtk_vsx_set_lpm(struct
> ufs_hba *hba, bool lpm)
>  
>  static void ufs_mtk_dev_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
>  {
> -	if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
> -		return;
> +	bool skip_vccqx = false;
>  
> -	/* Skip if VCC is assumed always-on */
> -	if (!hba->vreg_info.vcc)
> -		return;
> -
> -	/* Bypass LPM when device is still active */
> +	/* Prevent entering LPM when device is still active */
>  	if (lpm && ufshcd_is_ufs_dev_active(hba))
>  		return;
>  
> -	/* Bypass LPM if VCC is enabled */
> -	if (lpm && hba->vreg_info.vcc->enabled)
> -		return;
> +	/* Skip vccqx lpm control and control vsx only */
> +	if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
> +		skip_vccqx = true;
> +
> +	/* VCC is always-on, control vsx only */
> +	if (!hba->vreg_info.vcc)
> +		skip_vccqx = true;
> +
> +	/* Broken vcc keep vcc always on, most case control vsx only */
> +	if (lpm && hba->vreg_info.vcc && hba->vreg_info.vcc->enabled) {
> +		/* Some device vccqx/vsx can enter lpm */
> +		if (ufs_mtk_is_allow_vccqx_lpm(hba))
> +			skip_vccqx = false;
> +		else /* control vsx only */
> +			skip_vccqx = true;
> +	}
>  
>  	if (lpm) {
> -		ufs_mtk_vccqx_set_lpm(hba, lpm);
> +		if (!skip_vccqx)
> +			ufs_mtk_vccqx_set_lpm(hba, lpm);
>  		ufs_mtk_vsx_set_lpm(hba, lpm);
>  	} else {
>  		ufs_mtk_vsx_set_lpm(hba, lpm);
> -		ufs_mtk_vccqx_set_lpm(hba, lpm);
> +		if (!skip_vccqx)
> +			ufs_mtk_vccqx_set_lpm(hba, lpm);
>  	}
>  }
>  
> diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-
> mediatek.h
> index f76e80d91729..0720da2f1402 100644
> --- a/drivers/ufs/host/ufs-mediatek.h
> +++ b/drivers/ufs/host/ufs-mediatek.h
> @@ -136,6 +136,11 @@ enum ufs_mtk_host_caps {
>  	UFS_MTK_CAP_VA09_PWR_CTRL              = 1 << 1,
>  	UFS_MTK_CAP_DISABLE_AH8                = 1 << 2,
>  	UFS_MTK_CAP_BROKEN_VCC                 = 1 << 3,
> +
> +	/* Override UFS_MTK_CAP_BROKEN_VCC's behavior to
> +	 * allow vccqx upstream to enter LPM
> +	 */
> +	UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
>  	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
>  };
>  
Acked-by: Chun-Hung Wu <Chun-Hung.Wu@mediatek.com>

Re: [PATCH v1 2/7] ufs: host: mediatek: tx skew fix

[Bart Van Assche]

On 3/7/24 23:02, peter.wang@mediatek.com wrote:
> +static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba)
> +{
> +	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +
> +	return !!(host->caps & UFS_MTK_CAP_TX_SKEW_FIX);
> +}

Same comment here - please leave out the !!

Thanks,

Bart.

Re: [PATCH v1 2/7] ufs: host: mediatek: tx skew fix

[Chun-Hung Wu (巫駿宏)]

On Fri, 2024-03-08 at 15:02 +0800, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> Mediatek tx skew issue fix by check dts setting and vendor/model.
> Then set PA_TACTIVATE set 8
> 
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> ---
>  drivers/ufs/host/ufs-mediatek.c | 21 +++++++++++++++++++++
>  drivers/ufs/host/ufs-mediatek.h |  1 +
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-
> mediatek.c
> index 6fc6fa2ea5bd..0262e8994236 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -119,6 +119,13 @@ static bool ufs_mtk_is_pmc_via_fastauto(struct
> ufs_hba *hba)
>  	return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);
>  }
>  
> +static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba)
> +{
> +	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +
> +	return !!(host->caps & UFS_MTK_CAP_TX_SKEW_FIX);
> +}
> +
>  static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
>  {
>  	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> @@ -630,6 +637,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba
> *hba)
>  	if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto"))
>  		host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO;
>  
> +	if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))
> +		host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;
> +
>  	dev_info(hba->dev, "caps: 0x%x", host->caps);
>  }
>  
> @@ -1423,6 +1433,17 @@ static int ufs_mtk_apply_dev_quirks(struct
> ufs_hba *hba)
>  	if (mid == UFS_VENDOR_SAMSUNG) {
>  		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
>  		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10);
> +	} else if (mid == UFS_VENDOR_MICRON) {
> +		/* Only for the host which have TX skew issue */
> +		if (ufs_mtk_is_tx_skew_fix(hba) &&
> +			(STR_PRFX_EQUAL("MT128GBCAV2U31", dev_info-
> >model) ||
> +			STR_PRFX_EQUAL("MT256GBCAV4U31", dev_info-
> >model) ||
> +			STR_PRFX_EQUAL("MT512GBCAV8U31", dev_info-
> >model) ||
> +			STR_PRFX_EQUAL("MT256GBEAX4U40", dev_info-
> >model) ||
> +			STR_PRFX_EQUAL("MT512GAYAX4U40", dev_info-
> >model) ||
> +			STR_PRFX_EQUAL("MT001TAYAX8U40", dev_info-
> >model))) {
> +			ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
> 8);
> +		}
>  	}
>  
>  	/*
> diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-
> mediatek.h
> index 0720da2f1402..146c25080599 100644
> --- a/drivers/ufs/host/ufs-mediatek.h
> +++ b/drivers/ufs/host/ufs-mediatek.h
> @@ -142,6 +142,7 @@ enum ufs_mtk_host_caps {
>  	 */
>  	UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
>  	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
> +	UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
>  };
>  
>  struct ufs_mtk_crypt_cfg {

Acked-by: Chun-Hung Wu <Chun-Hung.Wu@mediatek.com>

Re: [PATCH v1 3/7] ufs: host: mediatek: Add UFS_MTK_CAP_DISABLE_MCQ

[Chun-Hung Wu (巫駿宏)]

On Fri, 2024-03-08 at 15:02 +0800, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> From: Po-Wen Kao <powen.kao@mediatek.com>
> 
> Add new mediatek host cap UFS_MTK_CAP_DISABLE_MCQ to allow disable
> MCQ feature by assigning dts boolean property
> "mediatek,ufs-disable-mcq""
> 
> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Po-Wen Kao <powen.kao@mediatek.com>
> ---
>  drivers/ufs/host/ufs-mediatek.c | 12 ++++++++++++
>  drivers/ufs/host/ufs-mediatek.h |  1 +
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-
> mediatek.c
> index 0262e8994236..cdf29cfa490b 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -640,6 +640,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba
> *hba)
>  	if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))
>  		host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;
>  
> +	if (of_property_read_bool(np, "mediatek,ufs-disable-mcq"))
> +		host->caps |= UFS_MTK_CAP_DISABLE_MCQ;
> +
>  	dev_info(hba->dev, "caps: 0x%x", host->caps);
>  }
>  
> @@ -874,6 +877,9 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba
> *hba)
>  	host->mcq_nr_intr = UFSHCD_MAX_Q_NR;
>  	pdev = container_of(hba->dev, struct platform_device, dev);
>  
> +	if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
> +		goto failed;
> +
>  	for (i = 0; i < host->mcq_nr_intr; i++) {
>  		/* irq index 0 is legacy irq, sq/cq irq start from
> index 1 */
>  		irq = platform_get_irq(pdev, i + 1);
> @@ -1585,6 +1591,12 @@ static int ufs_mtk_clk_scale_notify(struct
> ufs_hba *hba, bool scale_up,
>  
>  static int ufs_mtk_get_hba_mac(struct ufs_hba *hba)
>  {
> +	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +
> +	/* MCQ operation not permitted */
> +	if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
> +		return -EPERM;
> +
>  	return MAX_SUPP_MAC;
>  }
>  
> diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-
> mediatek.h
> index 146c25080599..79c64de25254 100644
> --- a/drivers/ufs/host/ufs-mediatek.h
> +++ b/drivers/ufs/host/ufs-mediatek.h
> @@ -143,6 +143,7 @@ enum ufs_mtk_host_caps {
>  	UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
>  	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
>  	UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
> +	UFS_MTK_CAP_DISABLE_MCQ                = 1 << 8,
>  };
>  
>  struct ufs_mtk_crypt_cfg {
Acked-by: Chun-Hung Wu <Chun-Hung.Wu@mediatek.com>

Re: [PATCH v1 4/7] ufs: host: mediatek: ufs mtk sip command reconstruct

[Bart Van Assche]

On 3/7/24 23:02, peter.wang@mediatek.com wrote:
> +/*
> + * SiP commands
> + */

An additional comment that explains what "SiP" means would be welcome.

Thanks,

Bart.

Re: [PATCH v1 4/7] ufs: host: mediatek: ufs mtk sip command reconstruct

[Chun-Hung Wu (巫駿宏)]

On Fri, 2024-03-08 at 15:02 +0800, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> From: Po-Wen Kao <powen.kao@mediatek.com>
> 
> Move sip command and define to a new sip header file.
> 
> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Po-Wen Kao <powen.kao@mediatek.com>
> ---
>  drivers/ufs/host/ufs-mediatek-sip.h | 90
> +++++++++++++++++++++++++++++
>  drivers/ufs/host/ufs-mediatek.c     |  3 +-
>  drivers/ufs/host/ufs-mediatek.h     | 79 -------------------------
>  3 files changed, 92 insertions(+), 80 deletions(-)
>  create mode 100755 drivers/ufs/host/ufs-mediatek-sip.h
> 
> diff --git a/drivers/ufs/host/ufs-mediatek-sip.h
> b/drivers/ufs/host/ufs-mediatek-sip.h
> new file mode 100755
> index 000000000000..30146bb1ccbe
> --- /dev/null
> +++ b/drivers/ufs/host/ufs-mediatek-sip.h
> @@ -0,0 +1,90 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +
> +#ifndef _UFS_MEDIATEK_SIP_H
> +#define _UFS_MEDIATEK_SIP_H
> +
> +#include <linux/soc/mediatek/mtk_sip_svc.h>
> +
> +/*
> + * SiP commands
> + */
> +#define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)
> +#define UFS_MTK_SIP_VA09_PWR_CTRL         BIT(0)
> +#define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
> +#define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
> +#define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
> +#define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)
> +#define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
> +#define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
> +
> +
> +/*
> + * Multi-VCC by Numbering
> + */
> +enum ufs_mtk_vcc_num {
> +	UFS_VCC_NONE = 0,
> +	UFS_VCC_1,
> +	UFS_VCC_2,
> +	UFS_VCC_MAX
> +};
> +
> +/*
> + * Host Power Control options
> + */
> +enum {
> +	HOST_PWR_HCI = 0,
> +	HOST_PWR_MPHY
> +};
> +
> +/*
> + * SMC call wrapper function
> + */
> +struct ufs_mtk_smc_arg {
> +	unsigned long cmd;
> +	struct arm_smccc_res *res;
> +	unsigned long v1;
> +	unsigned long v2;
> +	unsigned long v3;
> +	unsigned long v4;
> +	unsigned long v5;
> +	unsigned long v6;
> +	unsigned long v7;
> +};
> +
> +
> +static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
> +{
> +	arm_smccc_smc(MTK_SIP_UFS_CONTROL,
> +		s.cmd,
> +		s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);
> +}
> +
> +#define ufs_mtk_smc(...) \
> +	_ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})
> +
> +/* Sip kernel interface */
> +#define ufs_mtk_va09_pwr_ctrl(res, on) \
> +	ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)
> +
> +#define ufs_mtk_crypto_ctrl(res, enable) \
> +	ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)
> +
> +#define ufs_mtk_ref_clk_notify(on, stage, res) \
> +	ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on,
> stage)
> +
> +#define ufs_mtk_device_reset_ctrl(high, res) \
> +	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
> +
> +#define ufs_mtk_host_pwr_ctrl(opt, on, res) \
> +	ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
> +
> +#define ufs_mtk_get_vcc_num(res) \
> +	ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
> +
> +#define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \
> +	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on,
> ufs_version)
> +
> +#endif /* !_UFS_MEDIATEK_SIP_H */
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-
> mediatek.c
> index cdf29cfa490b..ae184e4f90e6 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -20,13 +20,14 @@
>  #include <linux/pm_qos.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/reset.h>
> -#include <linux/soc/mediatek/mtk_sip_svc.h>
>  
>  #include <ufs/ufshcd.h>
>  #include "ufshcd-pltfrm.h"
>  #include <ufs/ufs_quirks.h>
>  #include <ufs/unipro.h>
> +
>  #include "ufs-mediatek.h"
> +#include "ufs-mediatek-sip.h"
>  
>  static int  ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq);
>  
> diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-
> mediatek.h
> index 79c64de25254..17be3f748fa0 100644
> --- a/drivers/ufs/host/ufs-mediatek.h
> +++ b/drivers/ufs/host/ufs-mediatek.h
> @@ -8,7 +8,6 @@
>  
>  #include <linux/bitops.h>
>  #include <linux/pm_qos.h>
> -#include <linux/soc/mediatek/mtk_sip_svc.h>
>  
>  /*
>   * MCQ define and struct
> @@ -100,18 +99,6 @@ enum {
>  	VS_HIB_EXIT                 = 13,
>  };
>  
> -/*
> - * SiP commands
> - */
> -#define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)
> -#define UFS_MTK_SIP_VA09_PWR_CTRL         BIT(0)
> -#define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
> -#define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
> -#define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
> -#define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)
> -#define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
> -#define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
> -
>  /*
>   * VS_DEBUGCLOCKENABLE
>   */
> @@ -197,70 +184,4 @@ struct ufs_mtk_host {
>  	struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
>  };
>  
> -/*
> - * Multi-VCC by Numbering
> - */
> -enum ufs_mtk_vcc_num {
> -	UFS_VCC_NONE = 0,
> -	UFS_VCC_1,
> -	UFS_VCC_2,
> -	UFS_VCC_MAX
> -};
> -
> -/*
> - * Host Power Control options
> - */
> -enum {
> -	HOST_PWR_HCI = 0,
> -	HOST_PWR_MPHY
> -};
> -
> -/*
> - * SMC call wrapper function
> - */
> -struct ufs_mtk_smc_arg {
> -	unsigned long cmd;
> -	struct arm_smccc_res *res;
> -	unsigned long v1;
> -	unsigned long v2;
> -	unsigned long v3;
> -	unsigned long v4;
> -	unsigned long v5;
> -	unsigned long v6;
> -	unsigned long v7;
> -};
> -
> -static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
> -{
> -	arm_smccc_smc(MTK_SIP_UFS_CONTROL,
> -		      s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6,
> s.res);
> -}
> -
> -#define ufs_mtk_smc(...) \
> -	_ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})
> -
> -/*
> - * SMC call interface
> - */
> -#define ufs_mtk_va09_pwr_ctrl(res, on) \
> -	ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)
> -
> -#define ufs_mtk_crypto_ctrl(res, enable) \
> -	ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)
> -
> -#define ufs_mtk_ref_clk_notify(on, stage, res) \
> -	ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on,
> stage)
> -
> -#define ufs_mtk_device_reset_ctrl(high, res) \
> -	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
> -
> -#define ufs_mtk_host_pwr_ctrl(opt, on, res) \
> -	ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
> -
> -#define ufs_mtk_get_vcc_num(res) \
> -	ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
> -
> -#define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \
> -	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver)
> -
>  #endif /* !_UFS_MEDIATEK_H */

Acked-by: Chun-Hung Wu <Chun-Hung.Wu@mediatek.com>

Re: [PATCH v1 5/7] ufs: host: mediatek: rename host power control API

[Chun-Hung Wu (巫駿宏)]

On Fri, 2024-03-08 at 15:02 +0800, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> From: Po-Wen Kao <powen.kao@mediatek.com>
> 
> Host power control is control crypto sram power.
> Rename it for easy maintain.
> 
> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Po-Wen Kao <powen.kao@mediatek.com>
> ---
>  drivers/ufs/host/ufs-mediatek-sip.h | 13 +++----------
>  drivers/ufs/host/ufs-mediatek.c     |  4 ++--
>  2 files changed, 5 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek-sip.h
> b/drivers/ufs/host/ufs-mediatek-sip.h
> index 30146bb1ccbe..fd640846910a 100755
> --- a/drivers/ufs/host/ufs-mediatek-sip.h
> +++ b/drivers/ufs/host/ufs-mediatek-sip.h
> @@ -16,7 +16,7 @@
>  #define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
>  #define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
>  #define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
> -#define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)
> +#define UFS_MTK_SIP_SRAM_PWR_CTRL         BIT(5)
>  #define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
>  #define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
>  
> @@ -31,13 +31,6 @@ enum ufs_mtk_vcc_num {
>  	UFS_VCC_MAX
>  };
>  
> -/*
> - * Host Power Control options
> - */
> -enum {
> -	HOST_PWR_HCI = 0,
> -	HOST_PWR_MPHY
> -};
>  
>  /*
>   * SMC call wrapper function
> @@ -78,8 +71,8 @@ static inline void _ufs_mtk_smc(struct
> ufs_mtk_smc_arg s)
>  #define ufs_mtk_device_reset_ctrl(high, res) \
>  	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
>  
> -#define ufs_mtk_host_pwr_ctrl(opt, on, res) \
> -	ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
> +#define ufs_mtk_sram_pwr_ctrl(on, res) \
> +	ufs_mtk_smc(UFS_MTK_SIP_SRAM_PWR_CTRL, &(res), on)
>  
>  #define ufs_mtk_get_vcc_num(res) \
>  	ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-
> mediatek.c
> index ae184e4f90e6..2caf0c1d4e17 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -1376,7 +1376,7 @@ static int ufs_mtk_suspend(struct ufs_hba *hba,
> enum ufs_pm_op pm_op,
>  	if (ufshcd_is_link_off(hba))
>  		ufs_mtk_device_reset_ctrl(0, res);
>  
> -	ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, false, res);
> +	ufs_mtk_sram_pwr_ctrl(false, res);
>  
>  	return 0;
>  fail:
> @@ -1397,7 +1397,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba,
> enum ufs_pm_op pm_op)
>  	if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
>  		ufs_mtk_dev_vreg_set_lpm(hba, false);
>  
> -	ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, true, res);
> +	ufs_mtk_sram_pwr_ctrl(true, res);
>  
>  	err = ufs_mtk_mphy_power_on(hba, true);
>  	if (err)
Acked-by: Chun-Hung Wu <Chun-Hung.Wu@mediatek.com>

Re: [PATCH v1 6/7] ufs: host: mediatek: support mphy reset

[Chun-Hung Wu (巫駿宏)]

On Fri, 2024-03-08 at 15:02 +0800, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> This patch will reset mphy when host reset.
> Backup mphy setting after mphy reset control get.
> Restore mphy setting after mphy reset.
> 
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> ---
>  drivers/ufs/host/ufs-mediatek-sip.h |  9 ++++++++-
>  drivers/ufs/host/ufs-mediatek.c     | 14 ++++++++++++++
>  drivers/ufs/host/ufs-mediatek.h     |  1 +
>  3 files changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek-sip.h
> b/drivers/ufs/host/ufs-mediatek-sip.h
> index fd640846910a..64f48ecc54c7 100755
> --- a/drivers/ufs/host/ufs-mediatek-sip.h
> +++ b/drivers/ufs/host/ufs-mediatek-sip.h
> @@ -19,7 +19,7 @@
>  #define UFS_MTK_SIP_SRAM_PWR_CTRL         BIT(5)
>  #define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
>  #define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
> -
> +#define UFS_MTK_SIP_MPHY_CTRL             BIT(8)
>  
>  /*
>   * Multi-VCC by Numbering
> @@ -31,6 +31,10 @@ enum ufs_mtk_vcc_num {
>  	UFS_VCC_MAX
>  };
>  
> +enum ufs_mtk_mphy_op {
> +	UFS_MPHY_BACKUP = 0,
> +	UFS_MPHY_RESTORE
> +};
>  
>  /*
>   * SMC call wrapper function
> @@ -80,4 +84,7 @@ static inline void _ufs_mtk_smc(struct
> ufs_mtk_smc_arg s)
>  #define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \
>  	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on,
> ufs_version)
>  
> +#define ufs_mtk_mphy_ctrl(op, res) \
> +	ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op)
> +
>  #endif /* !_UFS_MEDIATEK_SIP_H */
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-
> mediatek.c
> index 2caf0c1d4e17..c4aae031b694 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -185,16 +185,23 @@ static void ufs_mtk_crypto_enable(struct
> ufs_hba *hba)
>  static void ufs_mtk_host_reset(struct ufs_hba *hba)
>  {
>  	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +	struct arm_smccc_res res;
>  
>  	reset_control_assert(host->hci_reset);
>  	reset_control_assert(host->crypto_reset);
>  	reset_control_assert(host->unipro_reset);
> +	reset_control_assert(host->mphy_reset);
>  
>  	usleep_range(100, 110);
>  
>  	reset_control_deassert(host->unipro_reset);
>  	reset_control_deassert(host->crypto_reset);
>  	reset_control_deassert(host->hci_reset);
> +	reset_control_deassert(host->mphy_reset);
> +
> +	/* restore mphy setting aftre mphy reset */
> +	if (host->mphy_reset)
> +		ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res);
>  }
>  
>  static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
> @@ -219,6 +226,8 @@ static void ufs_mtk_init_reset(struct ufs_hba
> *hba)
>  				   "unipro_rst");
>  	ufs_mtk_init_reset_control(hba, &host->crypto_reset,
>  				   "crypto_rst");
> +	ufs_mtk_init_reset_control(hba, &host->mphy_reset,
> +				   "mphy_rst");
>  }
>  
>  static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
> @@ -918,6 +927,7 @@ static int ufs_mtk_init(struct ufs_hba *hba)
>  	struct device *dev = hba->dev;
>  	struct ufs_mtk_host *host;
>  	int err = 0;
> +	struct arm_smccc_res res;
>  
>  	host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
>  	if (!host) {
> @@ -946,6 +956,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
>  
>  	ufs_mtk_init_reset(hba);
>  
> +	/* backup mphy setting if mphy can reset */
> +	if (host->mphy_reset)
> +		ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res);
> +
>  	/* Enable runtime autosuspend */
>  	hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
>  
> diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-
> mediatek.h
> index 17be3f748fa0..6129ab59e5f5 100644
> --- a/drivers/ufs/host/ufs-mediatek.h
> +++ b/drivers/ufs/host/ufs-mediatek.h
> @@ -166,6 +166,7 @@ struct ufs_mtk_host {
>  	struct reset_control *hci_reset;
>  	struct reset_control *unipro_reset;
>  	struct reset_control *crypto_reset;
> +	struct reset_control *mphy_reset;
>  	struct ufs_hba *hba;
>  	struct ufs_mtk_crypt_cfg *crypt;
>  	struct ufs_mtk_clk mclk;
Acked-by: Chun-Hung Wu <Chun-Hung.Wu@mediatek.com>

Re: [PATCH v1 5/7] ufs: host: mediatek: rename host power control API

[Bart Van Assche]

On 3/7/24 23:02, peter.wang@mediatek.com wrote:
> Host power control is control crypto sram power.

The above sentence is incomprehensible to me.

Thanks,

Bart.

Re: [PATCH v1 7/7] ufs: host: mediatek: support rtff in PM flow

[Chun-Hung Wu (巫駿宏)]

On Fri, 2024-03-08 at 15:02 +0800, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> From: Alice Chao <alice.chao@mediatek.com>
> 
> Reviewed-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Peter Wang <peter.wang@mediatek.com>
> Signed-off-by: Alice Chao <alice.chao@mediatek.com>
> ---
>  drivers/ufs/host/ufs-mediatek-sip.h |  4 ++++
>  drivers/ufs/host/ufs-mediatek.c     | 35
> +++++++++++++++++++++++++++++
>  drivers/ufs/host/ufs-mediatek.h     |  2 ++
>  3 files changed, 41 insertions(+)
> 
> diff --git a/drivers/ufs/host/ufs-mediatek-sip.h
> b/drivers/ufs/host/ufs-mediatek-sip.h
> index 64f48ecc54c7..eeab0f93146e 100755
> --- a/drivers/ufs/host/ufs-mediatek-sip.h
> +++ b/drivers/ufs/host/ufs-mediatek-sip.h
> @@ -20,6 +20,7 @@
>  #define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
>  #define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
>  #define UFS_MTK_SIP_MPHY_CTRL             BIT(8)
> +#define UFS_MTK_SIP_MTCMOS_CTRL           BIT(9)
>  
>  /*
>   * Multi-VCC by Numbering
> @@ -87,4 +88,7 @@ static inline void _ufs_mtk_smc(struct
> ufs_mtk_smc_arg s)
>  #define ufs_mtk_mphy_ctrl(op, res) \
>  	ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op)
>  
> +#define ufs_mtk_mtcmos_ctrl(op, res) \
> +	ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op)
> +
>  #endif /* !_UFS_MEDIATEK_SIP_H */
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-
> mediatek.c
> index c4aae031b694..2f191525c308 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -127,6 +127,13 @@ static bool ufs_mtk_is_tx_skew_fix(struct
> ufs_hba *hba)
>  	return !!(host->caps & UFS_MTK_CAP_TX_SKEW_FIX);
>  }
>  
> +static bool ufs_mtk_is_rtff_mtcmos(struct ufs_hba *hba)
> +{
> +	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +
> +	return !!(host->caps & UFS_MTK_CAP_RTFF_MTCMOS);
> +}
> +
>  static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
>  {
>  	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> @@ -653,6 +660,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba
> *hba)
>  	if (of_property_read_bool(np, "mediatek,ufs-disable-mcq"))
>  		host->caps |= UFS_MTK_CAP_DISABLE_MCQ;
>  
> +	if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos"))
> +		host->caps |= UFS_MTK_CAP_RTFF_MTCMOS;
> +
>  	dev_info(hba->dev, "caps: 0x%x", host->caps);
>  }
>  
> @@ -993,6 +1003,15 @@ static int ufs_mtk_init(struct ufs_hba *hba)
>  	 * Enable phy clocks specifically here.
>  	 */
>  	ufs_mtk_mphy_power_on(hba, true);
> +
> +	if (ufs_mtk_is_rtff_mtcmos(hba)) {
> +		/* First Restore here, to avoid backup unexpected value
> */
> +		ufs_mtk_mtcmos_ctrl(false, res);
> +
> +		/* Power on to init */
> +		ufs_mtk_mtcmos_ctrl(true, res);
> +	}
> +
>  	ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
>  
>  	host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
> @@ -1823,6 +1842,7 @@ static void ufs_mtk_remove(struct
> platform_device *pdev)
>  static int ufs_mtk_system_suspend(struct device *dev)
>  {
>  	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	struct arm_smccc_res res;
>  	int ret;
>  
>  	ret = ufshcd_system_suspend(dev);
> @@ -1831,15 +1851,22 @@ static int ufs_mtk_system_suspend(struct
> device *dev)
>  
>  	ufs_mtk_dev_vreg_set_lpm(hba, true);
>  
> +	if (ufs_mtk_is_rtff_mtcmos(hba))
> +		ufs_mtk_mtcmos_ctrl(false, res);
> +
>  	return 0;
>  }
>  
>  static int ufs_mtk_system_resume(struct device *dev)
>  {
>  	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	struct arm_smccc_res res;
>  
>  	ufs_mtk_dev_vreg_set_lpm(hba, false);
>  
> +	if (ufs_mtk_is_rtff_mtcmos(hba))
> +		ufs_mtk_mtcmos_ctrl(true, res);
> +
>  	return ufshcd_system_resume(dev);
>  }
>  #endif
> @@ -1848,6 +1875,7 @@ static int ufs_mtk_system_resume(struct device
> *dev)
>  static int ufs_mtk_runtime_suspend(struct device *dev)
>  {
>  	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	struct arm_smccc_res res;
>  	int ret = 0;
>  
>  	ret = ufshcd_runtime_suspend(dev);
> @@ -1856,12 +1884,19 @@ static int ufs_mtk_runtime_suspend(struct
> device *dev)
>  
>  	ufs_mtk_dev_vreg_set_lpm(hba, true);
>  
> +	if (ufs_mtk_is_rtff_mtcmos(hba))
> +		ufs_mtk_mtcmos_ctrl(false, res);
> +
>  	return 0;
>  }
>  
>  static int ufs_mtk_runtime_resume(struct device *dev)
>  {
>  	struct ufs_hba *hba = dev_get_drvdata(dev);
> +	struct arm_smccc_res res;
> +
> +	if (ufs_mtk_is_rtff_mtcmos(hba))
> +		ufs_mtk_mtcmos_ctrl(true, res);
>  
>  	ufs_mtk_dev_vreg_set_lpm(hba, false);
>  
> diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-
> mediatek.h
> index 6129ab59e5f5..599fea66663b 100644
> --- a/drivers/ufs/host/ufs-mediatek.h
> +++ b/drivers/ufs/host/ufs-mediatek.h
> @@ -131,6 +131,8 @@ enum ufs_mtk_host_caps {
>  	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
>  	UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
>  	UFS_MTK_CAP_DISABLE_MCQ                = 1 << 8,
> +	/* Control MTCMOS with RTFF */
> +	UFS_MTK_CAP_RTFF_MTCMOS                = 1 << 9,
>  };
>  
>  struct ufs_mtk_crypt_cfg {

Acked-by: Chun-Hung Wu <Chun-Hung.Wu@mediatek.com>

Re: [PATCH v1 1/7] ufs: host: mediatek: fix vsx/vccqx control logic

[Peter Wang (王信友)]

On Thu, 2024-03-14 at 19:33 -0700, Bart Van Assche wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 3/7/24 23:02, peter.wang@mediatek.com wrote:
> > +static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
> > +{
> > +struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> > +
> > +return !!(host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);
> > +}
> 
> Please leave out the !!. The compiler does this for you when
> implicitly 
> converting an int into a bool.
> 
> Thanks,
> 
> Bart.
> 

Hi Bart,

Will remove "!!" next version

Thanks.
Peter

Re: [PATCH v1 4/7] ufs: host: mediatek: ufs mtk sip command reconstruct

[Peter Wang (王信友)]

On Thu, 2024-03-14 at 19:36 -0700, Bart Van Assche wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 3/7/24 23:02, peter.wang@mediatek.com wrote:
> > +/*
> > + * SiP commands
> > + */
> 
> An additional comment that explains what "SiP" means would be
> welcome.
> 
> Thanks,
> 
> Bart.
> 

Hi Bart,

It means Silcon Partner.
Will add comment next version.

Thanks.
Peter

Re: [PATCH v1 5/7] ufs: host: mediatek: rename host power control API

[Peter Wang (王信友)]

On Thu, 2024-03-14 at 19:40 -0700, Bart Van Assche wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 3/7/24 23:02, peter.wang@mediatek.com wrote:
> > Host power control is control crypto sram power.
> 
> The above sentence is incomprehensible to me.
> 
> Thanks,
> 
> Bart.

Hi Bart,

It is medaitek host design.
Will add more description next version.

Thanks.
Peter