Re: [PATCH 3/3] soc: mediatek: pwrap: add mt6572 support

[AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>]

On 7/14/26 14:42, Roman Vivchar via B4 Relay wrote:
> From: Roman Vivchar <rva333@protonmail.com>
> 
> Add mt6572 registers and platform data for the pmic wrapper.
> The mt2701 SoC-specific initialization function is used because they
> share the same GPS_INTF settings.
> 


> Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> ---
>   drivers/soc/mediatek/mtk-pmic-wrap.c | 111 +++++++++++++++++++++++++++++++++++
>   1 file changed, 111 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index a4b10b0a97cb..4b8a5dc80a36 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -569,6 +569,96 @@ static const int mt2701_regs[] = {
>   	[PWRAP_ADC_RDATA_ADDR2] =	0x154,
>   };
>   

..snip..

>   
> +static const struct pmic_wrapper_type pwrap_mt6572 = {
> +	.regs = mt6572_regs,

MT6572 only has PWRAP_OP_TYPE, PWRAP_MSB_FIRST, PWRAP_GPS_STA additional registers
compared to MT2701, and the three are currently unused.

Instead of adding yet one more huge array for 3 more registers, since I'm mostly
sure that those will never be used anyway (happy if you prove me wrong!), you can
at this point just use mt2701_regs for mt6572.

Perhaps, add a comment saying that MT6572 does indeed have those additional regs
but were omitted because currently unused.

So, something like

/*
  * MT6572 has additional registers OP_TYPE (0x10), MSB_FIRST (0x14), GPS_STA (0x40)
  * which were omitted as they're currently unused in this driver.
  * Apart from that, the register map matches the one from MT2701.
  */
static const struct pmic_wrapper_type pwrap_mt6572 = {
	.regs = mt2701_regs,

Cheers,
Angelo

> +	.type = PWRAP_MT6572,
> +	.arb_en_all = 0x1ff,
> +	.int_en_all = 0x7ffffffd,
> +	.int1_en_all = 0,
> +	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
> +	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
> +	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
> +	.init_reg_clock = pwrap_common_init_reg_clock,
> +	.init_soc_specific = pwrap_mt2701_init_soc_specific,
> +};
> +
>   static const struct pmic_wrapper_type pwrap_mt6765 = {
>   	.regs = mt6765_regs,
>   	.type = PWRAP_MT6765,
> @@ -2446,6 +2556,7 @@ static const struct pmic_wrapper_type pwrap_mt8186 = {
>   
>   static const struct of_device_id of_pwrap_match_tbl[] = {
>   	{ .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 },
> +	{ .compatible = "mediatek,mt6572-pwrap", .data = &pwrap_mt6572 },
>   	{ .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 },
>   	{ .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 },
>   	{ .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 },
>