From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Bo-Chen Chen <rex-bc.chen@mediatek.com>,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
matthias.bgg@gmail.com
Cc: jason-jh.lin@mediatek.com, nancy.lin@mediatek.com,
ck.hu@mediatek.com, chunkuang.hu@kernel.org,
angelogioacchino.delregno@collabora.com, hsinyi@google.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
Date: Thu, 25 Aug 2022 09:11:33 +0300 [thread overview]
Message-ID: <3ff08ae9-a4b6-2b74-23cb-69ea1d7e1033@linaro.org> (raw)
In-Reply-To: <20220825055658.12429-1-rex-bc.chen@mediatek.com>
On 25/08/2022 08:56, Bo-Chen Chen wrote:
> From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
>
> For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> pipelines binding to 1 mmsys with the same power domain, the same
> clock driver and the same mediatek-drm driver.
>
> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
> 2 different power domains, different clock drivers and different
> mediatek-drm drivers.
I don't see binding to different clock drivers and anyway that's not
really an argument here. Please focus in description on hardware
properties, IOW, are devices compatible or different. What is the
incompatible difference between VDOSYS0 and 1?
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-08-25 6:13 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-25 5:56 [PATCH] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 Bo-Chen Chen
2022-08-25 6:11 ` Krzysztof Kozlowski [this message]
2022-08-25 6:59 ` Bo-Chen Chen
2022-08-25 8:13 ` Krzysztof Kozlowski
2022-08-25 10:55 ` Matthias Brugger
2022-08-25 11:06 ` Bo-Chen Chen
2022-08-25 13:03 ` Matthias Brugger
2022-08-25 10:56 ` Matthias Brugger
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