From: Krzysztof Kozlowski <krzk@kernel.org>
To: Laura Nao <laura.nao@collabora.com>,
mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de,
richardcochran@gmail.com
Cc: guangjie.song@mediatek.com, wenst@chromium.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
kernel@collabora.com,
"Nícolas F . R . A . Prado" <nfraprado@collabora.com>
Subject: Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers
Date: Sun, 3 Aug 2025 10:15:47 +0200 [thread overview]
Message-ID: <46590c06-a9e5-4469-873a-ec312f70cc9a@kernel.org> (raw)
In-Reply-To: <20250730105653.64910-10-laura.nao@collabora.com>
On 30/07/2025 12:56, Laura Nao wrote:
> +
> + mediatek,hardware-voter:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function
> + MCU manages clock and power domain control across the AP and other
> + remote processors. By aggregating their votes, it ensures clocks are
> + safely enabled/disabled and power domains are active before register
> + access.
No improvements, I already commented on this.
I also said:
"I already commented on this, so don't send v3 with the same."
NAK
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-08-03 8:18 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-30 10:56 [PATCH v3 00/27] Add support for MT8196 clock controllers Laura Nao
2025-07-30 10:56 ` [PATCH v3 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-07-30 10:56 ` [PATCH v3 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-07-30 10:56 ` [PATCH v3 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-07-30 10:56 ` [PATCH v3 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-07-30 10:56 ` [PATCH v3 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-08-04 14:05 ` Krzysztof Kozlowski
2025-08-04 14:33 ` AngeloGioacchino Del Regno
2025-07-30 10:56 ` [PATCH v3 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-07-30 10:56 ` [PATCH v3 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-07-30 10:56 ` [PATCH v3 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-07-30 10:56 ` [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers Laura Nao
2025-08-01 13:57 ` Rob Herring
2025-08-03 8:17 ` Krzysztof Kozlowski
2025-08-04 8:35 ` Laura Nao
2025-08-04 9:16 ` Krzysztof Kozlowski
2025-08-04 9:27 ` AngeloGioacchino Del Regno
2025-08-04 11:01 ` Krzysztof Kozlowski
2025-08-04 13:27 ` AngeloGioacchino Del Regno
2025-08-04 13:58 ` Krzysztof Kozlowski
2025-08-04 14:15 ` AngeloGioacchino Del Regno
2025-08-04 14:21 ` Krzysztof Kozlowski
2025-08-04 14:25 ` AngeloGioacchino Del Regno
2025-08-04 14:19 ` Krzysztof Kozlowski
2025-08-04 14:31 ` AngeloGioacchino Del Regno
2025-08-04 14:33 ` Krzysztof Kozlowski
2025-08-04 14:35 ` AngeloGioacchino Del Regno
2025-08-03 8:15 ` Krzysztof Kozlowski [this message]
2025-07-30 10:56 ` [PATCH v3 10/27] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-07-30 10:56 ` [PATCH v3 11/27] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-07-30 10:56 ` [PATCH v3 12/27] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 13/27] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-07-30 10:56 ` [PATCH v3 14/27] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-07-30 10:56 ` [PATCH v3 15/27] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 16/27] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 17/27] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-07-30 10:56 ` [PATCH v3 18/27] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-07-30 10:56 ` [PATCH v3 19/27] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 20/27] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-07-30 10:56 ` [PATCH v3 21/27] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 22/27] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 23/27] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-07-30 10:56 ` [PATCH v3 24/27] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 25/27] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 26/27] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 27/27] clk: mediatek: Add MT8196 vencsys " Laura Nao
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