From: Matthias Brugger <matthias.bgg@gmail.com>
To: Yongqiang Niu <yongqiang.niu@mediatek.com>,
Matthias Brugger <matthias.bgg@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Daniel Vetter <daniel@ffwll.ch>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Philipp Zabel <p.zabel@pengutronix.de>,
CK Hu <ck.hu@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function
Date: Fri, 29 Jan 2021 16:35:12 +0100 [thread overview]
Message-ID: <4cadc9f0-0761-7609-abac-d2211b097bda@gmail.com> (raw)
In-Reply-To: <1611190616.22801.6.camel@mhfsdcap03>
On 21/01/2021 01:56, Yongqiang Niu wrote:
> On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
>> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
>>> move register operation into mmsys path select function
>>
>> Why do you want to do that. It seems the register access pattern is the
>> same for all SoCs so far supported, so I don't see the need to duplicate
>> the code in every SoC.
>>
>> Regards,
>> Matthias
>
> mt2701 and mt8173 ovl mout en already different.
> mt2701 ovl mout en register offset is 0x30
> mt8173 olv mout en register offset is 0x40
>
> only the use case is different;
> mt2701 ovl->color0
> mt8173 ovl->rmda0
> there make different define for this different.
>
> #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
>
> #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
>
> for the future mt8183, ovl mout en register offset will change to
> 0xf00
>
> this is only one different sample, there will be more and more
> different, so we add this patch for different soc
>
>
That does not explain why you want to put the read and write calls in a per SoC
part, they are the same for all supported SoCs.
Anyway after having a second thought, I don't like this approach at all. I think
splitting up the code in several SoCs to not bloat the driver is a good thing,
but not as it is done in this series.
I'd prefer to use a lookup table as Enric did in his first approach [1]. We
could then add this table in a per SoC header file.
Regards,
Matthias
https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-5-enric.balletbo@collabora.com/
>>
>>>
>>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>> ---
>>> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +++++++++++++++++----------------
>>> 1 file changed, 71 insertions(+), 69 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> index 6c03282..64c8030 100644
>>> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> @@ -106,141 +106,161 @@ struct mtk_mmsys {
>>> .clk_driver = "clk-mt8183-mm",
>>> };
>>>
>>> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>> - enum mtk_ddp_comp_id next,
>>> - unsigned int *addr)
>>> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
>>> + enum mtk_ddp_comp_id cur,
>>> + enum mtk_ddp_comp_id next,
>>> + bool enable)
>>> {
>>> - unsigned int value;
>>> + unsigned int addr, value, reg;
>>>
>>> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> value = OVL0_MOUT_EN_COLOR0;
>>> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> value = OVL_MOUT_EN_RDMA;
>>> } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD_MOUT_EN_RDMA0;
>>> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> value = UFOE_MOUT_EN_DSI0;
>>> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> value = OVL1_MOUT_EN_COLOR1;
>>> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> value = GAMMA_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD1_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DSI3;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DSI3;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> value = RDMA1_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> + addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> value = RDMA2_SOUT_DSI3;
>>> } else {
>>> value = 0;
>>> }
>>>
>>> - return value;
>>> + if (value) {
>>> + reg = readl_relaxed(config_regs + addr);
>>> +
>>> + if (enable)
>>> + reg |= value;
>>> + else
>>> + reg &= ~value;
>>> +
>>> + writel_relaxed(reg, config_regs + addr);
>>> + }
>>> }
>>>
>>> -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>> - enum mtk_ddp_comp_id next,
>>> - unsigned int *addr)
>>> +static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
>>> + enum mtk_ddp_comp_id cur,
>>> + enum mtk_ddp_comp_id next,
>>> + bool enable)
>>> {
>>> - unsigned int value;
>>> + unsigned int addr, value, reg;
>>>
>>> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> value = COLOR0_SEL_IN_OVL0;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI0_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI1_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI0_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI1_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI2_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI3_SEL_IN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI0_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> - *addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> value = DPI1_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI0_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> - *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> value = DSI1_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI2_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> - *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> value = DSI3_SEL_IN_RDMA2;
>>> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> + addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> value = COLOR1_SEL_IN_OVL1;
>>> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> - *addr = DISP_REG_CONFIG_DSI_SEL;
>>> + addr = DISP_REG_CONFIG_DSI_SEL;
>>> value = DSI_SEL_IN_BLS;
>>> } else {
>>> value = 0;
>>> }
>>>
>>> - return value;
>>> + if (value) {
>>> + reg = readl_relaxed(config_regs + addr);
>>> +
>>> + if (enable)
>>> + reg |= value;
>>> + else
>>> + reg &= ~value;
>>> +
>>> + writel_relaxed(reg, config_regs + addr);
>>> + }
>>> }
>>>
>>> static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>>> @@ -265,21 +285,12 @@ void mtk_mmsys_ddp_connect(struct device *dev,
>>> enum mtk_ddp_comp_id next)
>>> {
>>> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
>>> - unsigned int addr, value, reg;
>>>
>>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) | value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, true);
>>>
>>> mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
>>>
>>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) | value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, true);
>>> }
>>> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>>>
>>> @@ -288,19 +299,10 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>>> enum mtk_ddp_comp_id next)
>>> {
>>> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
>>> - unsigned int addr, value, reg;
>>>
>>> - value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_mout_en(mmsys->regs, cur, next, false);
>>>
>>> - value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> - if (value) {
>>> - reg = readl_relaxed(mmsys->regs + addr) & ~value;
>>> - writel_relaxed(reg, mmsys->regs + addr);
>>> - }
>>> + mtk_mmsys_ddp_sel_in(mmsys->regs, cur, next, false);
>>> }
>>> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>>>
>>> --
>>> 1.8.1.1.dirty
>>> _______________________________________________
>>> Linux-mediatek mailing list
>>> Linux-mediatek@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
_______________________________________________
Linux-mediatek mailing list
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next prev parent reply other threads:[~2021-01-29 15:35 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-05 3:06 [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder Yongqiang Niu
2021-02-09 15:38 ` Enric Balletbo Serra
2021-02-10 11:59 ` Matthias Brugger
2021-01-05 3:06 ` [PATCH v4, 02/10] soc: mediatek: mmsys: Create struct mtk_mmsys to store context data Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function Yongqiang Niu
2021-01-20 19:38 ` Matthias Brugger
2021-01-21 0:56 ` Yongqiang Niu
2021-01-29 15:35 ` Matthias Brugger [this message]
2021-01-05 3:06 ` [PATCH v4, 04/10] soc: mediatek: mmsys: Use function call for setting the routing registers Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 05/10] soc: mediatek: mmsys: add mt8183 " Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 06/10] soc: mediatek: mmsys: add component OVL_2L2 Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 07/10] soc: mediatek: mmsys: add component POSTMASK Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4 Yongqiang Niu
2021-03-22 15:08 ` Chun-Kuang Hu
2021-01-05 3:06 ` [PATCH v4, 09/10] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register Yongqiang Niu
2021-01-05 3:06 ` [PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support Yongqiang Niu
2021-01-06 16:36 ` Chun-Kuang Hu
2021-01-19 4:16 ` [PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers Hsin-Yi Wang
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