Re: [PATCH v3 00/12] PHY: MediaTek DP PHY refactor and MT8196 eDP

[AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>]

On 7/7/26 17:42, AngeloGioacchino Del Regno wrote:
> Changes in v3:
>   - Added missing bitfield.h, pm_runtime.h includes (Sashiko)
>   - Set calibration data before registering PHY (Sashiko)
>   - Enable PM Runtime before creating PHY device (Sashiko)
>   - Continue poweroff if some write fails, but still return failure
>     as that would be a partial poweroff anyway (Sashiko)
>   - Added zero driving params to fix default calibration data setting (Sashiko)
>   - Added NULL check on device_Get_match_data (Sashiko)
> 

PHY maintainers, gentle ping.

Cheers,
Angelo


> Changes in v2:
>   - Fixed register offsets for ANA phy in MT8196
>   - Set/clear FORCE_VOLT_SWING_EN bit when configuring and resetting
>     the voltage swing registers
>   - Fixed endianness issue in call to nvmem_read_u16 (Sashiko)
>   - Added early exit during lanes disablement if none are enabled to
>     avoid out-of-bounds bitwise shift (Sashiko)
>   - Removed useless call to pm_runtime_get_sync() in probe(), which
>     also fixes issues pointed out by Sashiko
>   - Fixed wrong dig vs ana register array usage in power_on/off (Sashiko)
> 
> 
> This series performs major refactoring on the MediaTek DisplayPort PHY
> driver, makes it probe with devicetree instead of getting registered
> by the mtk_dp DRM driver, adds power_on/off() callbacks, and honors
> the phy configure opts' set_lanes and set_voltages for, respectively,
> varying the number of lanes and setting the voltage pre-emphasis and
> swing on the PHY, for each lane.
> 
> This driver now also properly gets the PHY (EYE) Calibration Data from
> NVMEM (eFuse array) if provided, instead of getting it (improperly)
> injected by the mtk_dp driver.
> 
> Additionally, all of the driving parameters calculations and most of
> the other register definitions were refactored to greatly enhance the
> human readability of this code.
> 
> As a last step, this also transfers the register offsets for both the
> digital and analog phy registers in arrays assigned to soc specific
> data, in an effort to both introduce support for new minor revisions
> of the MediaTek DisplayPort PHY and to have a clearer view of the
> register related differences between those (for example, it is easily
> understandable that the analog part remained exactly the same between
> MT8195 and MT8196, but the digital part gets a slight update).
> 
> Speaking of which, as a last step, this also adds support for the
> MT8196 SoC (and its derivatives), which uses this PHY only for its
> Embedded DisplayPort (eDP) IP (spoiler: the DP one seems to be way
> too different and requiring an entirely new PHY driver).
> 
> In this state, this driver can also easily support the MT8189 SoC
> with a few lines of code: even though I do have clean code to add
> support for this one, I was not (*yet*) able to test it on upstream
> based kernels, and for this reason I decided to leave that one out
> for now (but it's coming later for sure).
> 
> NOTE!
> Despite all the apparently breaking changes in the refactoring, full
> compatibility with older MTK_DP driver and with old devicetrees was
> retained and carefully tested on multiple platforms!
> 
> P.S.: I am aware of the BUILD_DRIVING_PARAM_0( 0, 2, 4, 7) checkpatch
> warning and I didn't fix it in bigger favor of human readability.
> 
> AngeloGioacchino Del Regno (12):
>    dt-bindings: phy: Document MT8195 and MT8196 DisplayPort PHYs
>    phy: phy-mtk-dp: Rename regs to regmap in struct mtk_dp_phy
>    phy: phy-mtk-dp: Allow probing with devicetree match
>    phy: phy-mtk-dp: Migrate register offsets to SoC specific pdata
>    phy: phy-mtk-dp: Implement power_on and power_off PHY callbacks
>    phy: phy-mtk-dp: Support set_lanes in configure and properly cleanup
>    phy: phy-mtk-dp: Support setting volt swing and preemphasis values
>    phy: phy-mtk-dp: Add support for digital and analog calibration
>    phy: phy-mtk-dp: Rewrite and document default driving param macros
>    phy: phy-mtk-dp: Add bitrate register val definitions to SoC data
>    phy: phy-mtk-dp: Add PHYD Lane EN register mask to SoC data
>    phy: phy-mtk-dp: Add support for MT8196 eDP PHY
> 
>   .../bindings/phy/mediatek,mt8195-dp-phy.yaml  |  77 ++
>   drivers/phy/mediatek/phy-mtk-dp.c             | 882 ++++++++++++++++--
>   2 files changed, 862 insertions(+), 97 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt8195-dp-phy.yaml
>