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From: "Frank Wunderlich" Message-ID: <4dbc3dabfdbc3bdf6b8d411e62a27fa8988e3388@linux.dev> TLS-Required: No Subject: Re: [PATCH v4 net-next 5/5] net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap" To: "Vladimir Oltean" Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, "Daniel Golle" , "Horatiu Vultur" , "=?utf-8?B?QmriiJriiI9ybiBNb3Jr?=" , "Andrew Lunn" , "Heiner Kallweit" , "Russell King" , "David S. Miller" , "Eric Dumazet" , "Jakub Kicinski" , "Paolo Abeni" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Matthias Brugger" , "AngeloGioacchino Del Regno" , "Eric Woudstra" , "Alexander Couzens" , "Chester A. Unal" , "DENG Qingfang" , "Sean Wang" , "Felix Fietkau" In-Reply-To: <20260330190443.bol5vjfqqitz7kuo@skbuf> References: <20260119091220.1493761-1-vladimir.oltean@nxp.com> <20260119091220.1493761-6-vladimir.oltean@nxp.com> <20260326215404.krh6v3mmnqdlndli@skbuf> <20260330190443.bol5vjfqqitz7kuo@skbuf> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260401_225045_782150_807F28B7 X-CRM114-Status: GOOD ( 21.75 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, i tried using these properties in sgmiisys0 node (which should be mapped = to mac0 and the mt7530 switch) without success [1]. it looks like these properties are not read somewhere. the flow is mtk_probe (eth driver) if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { err =3D mtk_sgmii_init(eth); and there calling mtk_pcs_lynxi_create with the sgmiisys-node (for each m= ac, so imho mac0=3Dsgmiisys0) but handling the sgmiisys only as syscon, not a "real" pcs node [2]. but your new code calls phy_get_tx_polarity and should read out this prop= erties, but from subnode "pcs", so next try was &sgmiisys0 { pcs { rx-polarity =3D ; tx-polarity =3D ; }; }; which results in completely strange behaviour (looks like sgmiisys1 is ma= pped to mac0, but based on code in mtk_sgmii_init 0=3D0 should be right): [ 2.765218] SGMSYS_QPHY_WRAP_CTRL =3D 0x501, will write 0x500 [ 9.143849] SGMSYS_QPHY_WRAP_CTRL =3D 0x500, will write 0x501 but nevertheless i tried changing sgmiisys0 to sgmiisys1 and got the dame= result as before [ 2.713644] SGMSYS_QPHY_WRAP_CTRL =3D 0x501, will write 0x500 [ 9.061509] SGMSYS_QPHY_WRAP_CTRL =3D 0x500, will write 0x500 i can only change the second serdes with sgmiisys0, but not the first. mapping between mac and sgmiisys in dts in mt7986a.dtsi [3] are like this= : eth: ethernet@15100000 { compatible =3D "mediatek,mt7986-eth"; mediatek,sgmiisys =3D <&sgmiisys0>, <&sgmiisys1>; ... }; ð { status =3D "okay"; gmac0: mac@0 { compatible =3D "mediatek,eth-mac"; ... }; gmac1: mac@1 { compatible =3D "mediatek,eth-mac"; ... }; }; maybe it is time to revive the PCS framework discussion ([4]-[6])? [1] https://github.com/frank-w/BPI-Router-Linux/commit/4846a7bb352fe59111= 36cba33813f099bac035fd [2] https://elixir.bootlin.com/linux/v7.0-rc4/source/drivers/net/ethernet= /mediatek/mtk_eth_soc.c#L5001 [3] https://elixir.bootlin.com/linux/v7.0-rc4/source/arch/arm64/boot/dts/= mediatek/mt7986a.dtsi#L528 [4] * https://patchwork.kernel.org/project/netdevbpf/patch/20250610233134= .3588011-4-sean.anderson@linux.dev/ (v6) > pcs-framework itself had not yet got a response from netdev maintainer = (only other parts) [5] * https://patchwork.kernel.org/project/netdevbpf/patch/20250511201250= .3789083-4-ansuelsmth@gmail.com/ (v4) > discussion: https://lore.kernel.org/netdev/20250511201250.3789083-1-ans= uelsmth@gmail.com/ [6] * https://patchwork.kernel.org/project/netdevbpf/patch/ba4e359584a6b3= bc4b3470822c42186d5b0856f9.1721910728.git.daniel@makrotopia.org/ > discussion: https://patchwork.kernel.org/project/netdevbpf/patch/8aa905= 080bdb6760875d62cb3b2b41258837f80e.1702352117.git.daniel@makrotopia.org/ Am 30. M=C3=A4rz 2026 um 21:04 schrieb "Vladimir Oltean" : >=20 >=20Hi Frank, >=20 >=20On Mon, Mar 30, 2026 at 05:52:17PM +0000, Frank Wunderlich wrote: >=20 >=20>=20 >=20> Hi Vladimir > >=20=20 >=20> Thanks for the patch and sorry for my delay...i was away this week= end so i was not able to test. > >=20=20 >=20> traffic works again (but there is only read now) and this is the r= esult of your debug prints: > >=20=20 >=20> root@bpi-r3:~# mailto:root@bpi-r3:~# dmesg | grep SGMSYS_QPHY_WRA= P_CTRL > > [ 2.706963] SGMSYS_QPHY_WRAP_CTRL =3D 0x501, intending to write 0x50= 0 > > [ 9.134081] SGMSYS_QPHY_WRAP_CTRL =3D 0x500, intending to write 0x50= 0 > >=20=20 >=20> R3/mt7986 has 2 MAC, and switch is on the first, so value will cha= nge, not sure why this is different. > >=20=20 >=20> i have not found SGMSYS_QPHY_WRAP_CTRL or something related with p= olarity in ethernet/mac- > > (drivers/net/ethernet/mediatek/mtk_eth_soc.c) or switch-driver (driv= ers/net/dsa/mt7530{,-mdio}.c) > > in case they manipulate this register too (of course they should not= ). Also looked into the pcs-handling > > in both drivers, but see nothing related to polarity. And looked for= possible duplicate register const > > definition (other name for 0xec). > >=20 >=20This result means that your default QPHY_WRAP_CTRL register value has > the SGMII_PN_SWAP_TX bit set. Whether that comes from U-Boot or hardwar= e > default or otherwise, it doesn't really matter. Curious that the > SGMII_SW_RESET doesn't clear TX inversion, though. I guess you wouldn't > have documentation that would suggest this setting is sticky? >=20 >=20In Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml, > it is not specified what happens when the "mediatek,pnswap" property is > missing. I thought the most logical thing would be for the lane > polarities to not be swapped - because how would you describe normal > lane polarities otherwise? My bad for thinking the original vendor > bindings were more sane than they were. >=20 >=20The only way to describe the polarities that this SGMSYS block needs = on > a particular board is to use the newly introduced 'rx-polarity =3D > ' and 'tx-polarity =3D '. Which I stron= gly > recommend you to do, even if the attached patch should restore > functionality with your current device tree. >=20 regards=20Frank