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Wed, 23 Nov 2022 07:23:10 -0800 (PST) Message-ID: <5b253182-c15e-7fdd-48e2-37fd64838644@gmail.com> Date: Wed, 23 Nov 2022 16:23:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v2 2/5] arm64: dts: mt8186: Add power domains controller Content-Language: en-US To: Allen-KH Cheng , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, hsinyi@chromium.org References: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> <20221123135531.23221-3-allen-kh.cheng@mediatek.com> From: Matthias Brugger In-Reply-To: <20221123135531.23221-3-allen-kh.cheng@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221123_072315_108762_6AF40FDF X-CRM114-Status: GOOD ( 16.37 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On 23/11/2022 14:55, Allen-KH Cheng wrote: > Add power domains controller for mt8186 SoC. > > Signed-off-by: Allen-KH Cheng Applied for the next merge window. (v6.2-tmp/dts64 which will transform into v6.2-next/dts64 once v6.2-rc1 is released) Thanks > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 188 +++++++++++++++++++++++ > 1 file changed, 188 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index c326aeb33a10..2b03a342b8db 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -332,6 +332,194 @@ > #interrupt-cells = <2>; > }; > > + scpsys: syscon@10006000 { > + compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; > + reg = <0 0x10006000 0 0x1000>; > + > + /* System Power Manager */ > + spm: power-controller { > + compatible = "mediatek,mt8186-power-controller"; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + /* power domain of the SoC */ > + mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { > + reg = ; > + clocks = <&topckgen CLK_TOP_MFG>; > + clock-names = "mfg00"; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_MFG1 { > + reg = ; > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_MFG2 { > + reg = ; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_MFG3 { > + reg = ; > + #power-domain-cells = <0>; > + }; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { > + reg = ; > + clocks = <&topckgen CLK_TOP_SENINF>, > + <&topckgen CLK_TOP_SENINF1>; > + clock-names = "csirx_top0", "csirx_top1"; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_SSUSB { > + reg = ; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { > + reg = ; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_ADSP_AO { > + reg = ; > + clocks = <&topckgen CLK_TOP_AUDIODSP>, > + <&topckgen CLK_TOP_ADSP_BUS>; > + clock-names = "audioadsp", "adsp_bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { > + reg = ; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { > + reg = ; > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CONN_ON { > + reg = ; > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_DIS { > + reg = ; > + clocks = <&topckgen CLK_TOP_DISP>, > + <&topckgen CLK_TOP_MDP>, > + <&mmsys CLK_MM_SMI_INFRA>, > + <&mmsys CLK_MM_SMI_COMMON>, > + <&mmsys CLK_MM_SMI_GALS>, > + <&mmsys CLK_MM_SMI_IOMMU>; > + clock-names = "disp", "mdp", "smi_infra", "smi_common", > + "smi_gals", "smi_iommu"; > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_VDEC { > + reg = ; > + clocks = <&topckgen CLK_TOP_VDEC>, > + <&vdecsys CLK_VDEC_LARB1_CKEN>; > + clock-names = "vdec0", "larb"; > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CAM { > + reg = ; > + clocks = <&topckgen CLK_TOP_CAM>, > + <&topckgen CLK_TOP_SENINF>, > + <&topckgen CLK_TOP_SENINF1>, > + <&topckgen CLK_TOP_SENINF2>, > + <&topckgen CLK_TOP_SENINF3>, > + <&topckgen CLK_TOP_CAMTM>, > + <&camsys CLK_CAM2MM_GALS>; > + clock-names = "cam-top", "cam0", "cam1", "cam2", > + "cam3", "cam-tm", "gals"; > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { > + reg = ; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { > + reg = ; > + #power-domain-cells = <0>; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_IMG { > + reg = ; > + clocks = <&topckgen CLK_TOP_IMG1>, > + <&imgsys1 CLK_IMG1_GALS_IMG1>; > + clock-names = "img-top", "gals"; > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_IMG2 { > + reg = ; > + #power-domain-cells = <0>; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_IPE { > + reg = ; > + clocks = <&topckgen CLK_TOP_IPE>, > + <&ipesys CLK_IPE_LARB19>, > + <&ipesys CLK_IPE_LARB20>, > + <&ipesys CLK_IPE_SMI_SUBCOM>, > + <&ipesys CLK_IPE_GALS_IPE>; > + clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", > + "ipe-smi", "ipe-gals"; > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_VENC { > + reg = ; > + clocks = <&topckgen CLK_TOP_VENC>, > + <&vencsys CLK_VENC_CKE1_VENC>; > + clock-names = "venc0", "larb"; > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_WPE { > + reg = ; > + clocks = <&topckgen CLK_TOP_WPE>, > + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, > + <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; > + clock-names = "wpe0", "larb-ck", "larb-pclk"; > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + }; > + }; > + }; > + > watchdog: watchdog@10007000 { > compatible = "mediatek,mt8186-wdt", > "mediatek,mt6589-wdt";