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[93.34.89.13]) by smtp.gmail.com with ESMTPSA id t4-20020a0560001a4400b0032763287473sm13276997wry.75.2023.10.10.09.49.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 09:49:09 -0700 (PDT) Message-ID: <65258085.050a0220.dfda3.2518@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 10 Oct 2023 18:49:08 +0200 From: Christian Marangi To: Frank Wunderlich Cc: Bjorn Helgaas , Daniel Golle , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , Matthias Brugger , Bjorn Helgaas , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Lorenzo Pieralisi , Jianjun Wang , Ryder Lee , John Crispin Subject: Re: [PATCH] PCI: mediatek-gen3: fix PCIe #PERST being de-asserted too early References: <20231010160423.GA977719@bhelgaas> <1E611A63-AD66-4E61-90F9-F1DB41BD6466@fw-web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1E611A63-AD66-4E61-90F9-F1DB41BD6466@fw-web.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231010_094913_916451_5D522EDF X-CRM114-Status: GOOD ( 30.34 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Tue, Oct 10, 2023 at 06:42:07PM +0200, Frank Wunderlich wrote: > Am 10. Oktober 2023 18:04:23 MESZ schrieb Bjorn Helgaas : > >On Fri, Oct 06, 2023 at 09:45:58AM +0200, Daniel Golle wrote: > >> The driver for MediaTek gen3 PCIe hosts de-asserts all reset > >> signals at the same time using a single register write operation. > >> Delay the de-assertion of the #PERST signal by 100ms as required by > >> PCIe CEM clause 2.2, some PCIe devices fail to come up otherwise. > >> > >> Signed-off-by: Daniel Golle > >> --- > >> drivers/pci/controller/pcie-mediatek-gen3.c | 8 +++++++- > >> 1 file changed, 7 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > >> index e0e27645fdf4..ba8cfce03aad 100644 > >> --- a/drivers/pci/controller/pcie-mediatek-gen3.c > >> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > >> @@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) > > > >I feel like I'm missing something because this patch seems to be > >adding a delay for T_PVPERL, but the comment before the existing > >msleep() claims *it* is the T_PVPERL delay: > > > > * Described in PCIe CEM specification sections 2.2 (PERST# Signal) > > * and 2.2.1 (Initial Power-Up (G3 to S0)). > > * The deassertion of PERST# should be delayed 100ms (TPVPERL) > > * for the power and clock to become stable. > > > >> msleep(100); > >> > >> /* De-assert reset signals */ > >> - val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); > >> + val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB); > >> + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); > >> + > >> + msleep(100); > > > >So I'm confused about these two sleeps. Are they for different > >parameters? > > > >T_PVPERL is defined from "Power stable to PERST# inactive". Do we > >have any actual indication of when to start that delay, i.e., do we > >have a clue about when power became stable? > > > >> + /* De-assert PERST# signals */ > >> + val &= ~(PCIE_PE_RSTB); > >> writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); > >> > >> /* Check if the link is up or not */ > >> -- > >> 2.42.0 > >> > >> > >> _______________________________________________ > >> linux-arm-kernel mailing list > >> linux-arm-kernel@lists.infradead.org > >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > Hi > > Seems it is same as the patch i've sent some time ago and which was rejected because of the additional delay... > > https://patchwork.kernel.org/project/linux-mediatek/patch/20230402131347.99268-1-linux@fw-web.de/ > > Or am i wrong? > regards Frank Reading the other series, I smell this can only be handled by a quirk... This might be a defect or the board not following PCIE hw specs. Thing is that the bug/limitation is there and we have enough info to find way to fix this and lots of tester. Eventually even a fixup based on a specific compatible. -- Ansuel