[PATCH] PCI: mediatek-gen3: fix PCIe #PERST being de-asserted too early

[PATCH] PCI: mediatek-gen3: fix PCIe #PERST being de-asserted too early

[Daniel Golle]

The driver for MediaTek gen3 PCIe hosts de-asserts all reset
signals at the same time using a single register write operation.
Delay the de-assertion of the #PERST signal by 100ms as required by
PCIe CEM clause 2.2, some PCIe devices fail to come up otherwise.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index e0e27645fdf4..ba8cfce03aad 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
 	msleep(100);
 
 	/* De-assert reset signals */
-	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
+	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
+	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+
+	msleep(100);
+
+	/* De-assert PERST# signals */
+	val &= ~(PCIE_PE_RSTB);
 	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
 
 	/* Check if the link is up or not */
-- 
2.42.0

Re: [PATCH] PCI: mediatek-gen3: fix PCIe #PERST being de-asserted too early

[Bjorn Helgaas]

On Fri, Oct 06, 2023 at 09:45:58AM +0200, Daniel Golle wrote:
> The driver for MediaTek gen3 PCIe hosts de-asserts all reset
> signals at the same time using a single register write operation.
> Delay the de-assertion of the #PERST signal by 100ms as required by
> PCIe CEM clause 2.2, some PCIe devices fail to come up otherwise.
> 
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
>  drivers/pci/controller/pcie-mediatek-gen3.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index e0e27645fdf4..ba8cfce03aad 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)

I feel like I'm missing something because this patch seems to be
adding a delay for T_PVPERL, but the comment before the existing
msleep() claims *it* is the T_PVPERL delay:

         * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
         * and 2.2.1 (Initial Power-Up (G3 to S0)).
         * The deassertion of PERST# should be delayed 100ms (TPVPERL)
         * for the power and clock to become stable.

>  	msleep(100);
>  
>  	/* De-assert reset signals */
> -	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
> +	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
> +	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
> +
> +	msleep(100);

So I'm confused about these two sleeps.  Are they for different
parameters?

T_PVPERL is defined from "Power stable to PERST# inactive".  Do we
have any actual indication of when to start that delay, i.e., do we
have a clue about when power became stable?

> +	/* De-assert PERST# signals */
> +	val &= ~(PCIE_PE_RSTB);
>  	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
>  
>  	/* Check if the link is up or not */
> -- 
> 2.42.0
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH] PCI: mediatek-gen3: fix PCIe #PERST being de-asserted too early

[Christian Marangi]

On Tue, Oct 10, 2023 at 06:42:07PM +0200, Frank Wunderlich wrote:
> Am 10. Oktober 2023 18:04:23 MESZ schrieb Bjorn Helgaas <helgaas@kernel.org>:
> >On Fri, Oct 06, 2023 at 09:45:58AM +0200, Daniel Golle wrote:
> >> The driver for MediaTek gen3 PCIe hosts de-asserts all reset
> >> signals at the same time using a single register write operation.
> >> Delay the de-assertion of the #PERST signal by 100ms as required by
> >> PCIe CEM clause 2.2, some PCIe devices fail to come up otherwise.
> >> 
> >> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> >> ---
> >>  drivers/pci/controller/pcie-mediatek-gen3.c | 8 +++++++-
> >>  1 file changed, 7 insertions(+), 1 deletion(-)
> >> 
> >> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> >> index e0e27645fdf4..ba8cfce03aad 100644
> >> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> >> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> >> @@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
> >
> >I feel like I'm missing something because this patch seems to be
> >adding a delay for T_PVPERL, but the comment before the existing
> >msleep() claims *it* is the T_PVPERL delay:
> >
> >         * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
> >         * and 2.2.1 (Initial Power-Up (G3 to S0)).
> >         * The deassertion of PERST# should be delayed 100ms (TPVPERL)
> >         * for the power and clock to become stable.
> >
> >>  	msleep(100);
> >>  
> >>  	/* De-assert reset signals */
> >> -	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
> >> +	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
> >> +	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
> >> +
> >> +	msleep(100);
> >
> >So I'm confused about these two sleeps.  Are they for different
> >parameters?
> >
> >T_PVPERL is defined from "Power stable to PERST# inactive".  Do we
> >have any actual indication of when to start that delay, i.e., do we
> >have a clue about when power became stable?
> >
> >> +	/* De-assert PERST# signals */
> >> +	val &= ~(PCIE_PE_RSTB);
> >>  	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
> >>  
> >>  	/* Check if the link is up or not */
> >> -- 
> >> 2.42.0
> >> 
> >> 
> >> _______________________________________________
> >> linux-arm-kernel mailing list
> >> linux-arm-kernel@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> Hi
> 
> Seems it is same as the patch i've sent some time ago and which was rejected because of the additional delay...
> 
> https://patchwork.kernel.org/project/linux-mediatek/patch/20230402131347.99268-1-linux@fw-web.de/
> 
> Or am i wrong?
> regards Frank

Reading the other series, I smell this can only be handled by a quirk...
This might be a defect or the board not following PCIE hw specs.

Thing is that the bug/limitation is there and we have enough info to
find way to fix this and lots of tester.

Eventually even a fixup based on a specific compatible.

-- 
	Ansuel

Re: [PATCH] PCI: mediatek-gen3: fix PCIe #PERST being de-asserted too early

[Jianjun Wang (王建军)]

On Tue, 2023-10-10 at 18:42 +0200, Frank Wunderlich wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> Am 10. Oktober 2023 18:04:23 MESZ schrieb Bjorn Helgaas <
> helgaas@kernel.org>:
> > On Fri, Oct 06, 2023 at 09:45:58AM +0200, Daniel Golle wrote:
> > > The driver for MediaTek gen3 PCIe hosts de-asserts all reset
> > > signals at the same time using a single register write operation.
> > > Delay the de-assertion of the #PERST signal by 100ms as required
> > > by
> > > PCIe CEM clause 2.2, some PCIe devices fail to come up otherwise.
> > > 
> > > Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> > >  drivers/pci/controller/pcie-mediatek-gen3.c | 8 +++++++-
> > >  1 file changed, 7 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> > > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > > index e0e27645fdf4..ba8cfce03aad 100644
> > > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > > @@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct
> > > mtk_gen3_pcie *pcie)
> > > 
> > 
> > I feel like I'm missing something because this patch seems to be
> > adding a delay for T_PVPERL, but the comment before the existing
> > msleep() claims *it* is the T_PVPERL delay:
> > 
> >          * Described in PCIe CEM specification sections 2.2 (PERST#
> > Signal)
> >          * and 2.2.1 (Initial Power-Up (G3 to S0)).
> >          * The deassertion of PERST# should be delayed 100ms
> > (TPVPERL)
> >          * for the power and clock to become stable.
> > 
> > >  	msleep(100);
> > >  
> > >  	/* De-assert reset signals */
> > > -	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
> > > PCIE_PE_RSTB);
> > > +	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
> > > +	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
> > > +
> > > +	msleep(100);
> > > 
> > 
> > So I'm confused about these two sleeps.  Are they for different
> > parameters?
> > 
> > T_PVPERL is defined from "Power stable to PERST# inactive".  Do we
> > have any actual indication of when to start that delay, i.e., do we
> > have a clue about when power became stable?
> > 
> > > +	/* De-assert PERST# signals */
> > > +	val &= ~(PCIE_PE_RSTB);
> > >  	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
> > >  
> > >  	/* Check if the link is up or not */
> > > -- 
> > > 2.42.0
> > > linux-arm-kernel mailing list
> > > linux-arm-kernel@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> Hi
> 
> Seems it is same as the patch i've sent some time ago and which was
> rejected because of the additional delay...
> 
> 
https://patchwork.kernel.org/project/linux-mediatek/patch/20230402131347.99268-1-linux@fw-web.de/
> 
> Or am i wrong?
> regards Frank

Hi Daniel,

Did you found this issue on MT7986(BPI-R3) or other platforms?

Can you share the PCIe device model that failed to link up?

Thanks.