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(93-34-91-161.ip49.fastwebnet.it. [93.34.91.161]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae161b5sm13816130f8f.74.2024.11.18.10.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2024 10:35:22 -0800 (PST) Message-ID: <673b88ea.5d0a0220.17b04a.bc4b@mx.google.com> X-Google-Original-Message-ID: Date: Mon, 18 Nov 2024 19:35:18 +0100 From: Christian Marangi To: Vladimir Oltean Cc: Andrew Lunn , Florian Fainelli , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@airoha.com Subject: Re: [net-next PATCH v7 0/4] net: dsa: Add Airoha AN8855 support References: <20241117132811.67804-1-ansuelsmth@gmail.com> <20241118144859.4hwgpxtql5fplcyt@skbuf> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241118144859.4hwgpxtql5fplcyt@skbuf> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241118_103525_393864_23126999 X-CRM114-Status: GOOD ( 18.52 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, Nov 18, 2024 at 04:48:59PM +0200, Vladimir Oltean wrote: > Hi Christian, > > On Sun, Nov 17, 2024 at 02:27:55PM +0100, Christian Marangi wrote: > > This small series add the initial support for the Airoha AN8855 Switch. > > > > It's a 5 port Gigabit Switch with SGMII/HSGMII upstream port. > > > > This is starting to get in the wild and there are already some router > > having this switch chip. > > > > It's conceptually similar to mediatek switch but register and bits > > are different. And there is that massive Hell that is the PCS > > configuration. > > Saddly for that part we have absolutely NO documentation currently. > > > > There is this special thing where PHY needs to be calibrated with values > > from the switch efuse. (the thing have a whole cpu timer and MCU) > > Have you run the scripts in tools/testing/selftests/drivers/net/dsa/? > Could you post the results? Any test in particular? I'm working on adding correct support for them in OpenWrt. Should I expect some to fail? -- Ansuel