Re: Aw: [PATCH] PCI: mediatek-gen3: handle PERST after reset

["Jianjun Wang (王建军)" <Jianjun.Wang@mediatek.com>]

Hi Frank,

Seems this patch has huge impact on boot time, I'm curious about the
NVMe detection issue on mt7986, can you share the SSD model that you
are using and the bootup logs with that SSD?

Thanks.

On Wed, 2023-04-26 at 19:41 +0200, Frank Wunderlich wrote:
> External email : Please do not click links or open attachments until
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> 
> 
> Hi
> 
> > Gesendet: Sonntag, 02. April 2023 um 15:13 Uhr
> > Von: "Frank Wunderlich" <linux@fw-web.de>
> > De-assert PERST in separate step after reset signals to fully
> > comply
> > the PCIe CEM clause 2.2.
> > 
> > This fixes some NVME detection issues on mt7986.
> > 
> > Fixes: d3bf75b579b9 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver
> > for MT8192")
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > ---
> > Patch is taken from user Ruslan aka RRKh61 (permitted me to send it
> > with me as author).
> > 
> > 
https://urldefense.com/v3/__https://forum.banana-pi.org/t/bpi-r3-nvme-connection-issue/14563/17__;!!CTRNKA9wMg0ARbw!nCXEM685pkUpoiZYGKptPYccNrWMeN2D3jIO5_irwxZJ7c6ZzEeACIx-V2WeZHAP_0FKlDDIQ0RbDJ892prtoToDv30$
> > ---
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 8 +++++++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index b8612ce5f4d0..176b1a04565d 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct
> > mtk_gen3_pcie *pcie)
> >       msleep(100);
> > 
> >       /* De-assert reset signals */
> > -     val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
> > PCIE_PE_RSTB);
> > +     val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
> > +     writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
> > +
> > +     msleep(100);
> > +
> > +     /* De-assert PERST# signals */
> > +     val &= ~(PCIE_PE_RSTB);
> >       writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
> > 
> >       /* Check if the link is up or not */
> 
> Hi
> 
> just a friendly reminder....do i miss any recipient?
> 
> regards Frank
>