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Fri, 18 Mar 2022 15:02:33 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Mar 2022 15:02:33 +0800 Message-ID: <77a934c9a22d442b5dd00586ebc19157207c0d25.camel@mediatek.com> Subject: Re: [PATCH v16 4/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 From: CK Hu To: jason-jh.lin , Rob Herring , Matthias Brugger , "Chun-Kuang Hu" , Philipp Zabel , AngeloGioacchino Del Regno Date: Fri, 18 Mar 2022 15:02:33 +0800 In-Reply-To: <20220307032859.3275-5-jason-jh.lin@mediatek.com> References: <20220307032859.3275-1-jason-jh.lin@mediatek.com> <20220307032859.3275-5-jason-jh.lin@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220318_000251_987840_EBE8CDF8 X-CRM114-Status: GOOD ( 21.14 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Maxime Coquelin , David Airlie , linux-kernel@vger.kernel.org, singo.chang@mediatek.com, Alexandre Torgue , roy-cw.yeh@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com, Fabien Parent , moudy.ho@mediatek.com, linux-mediatek@lists.infradead.org, Daniel Vetter , hsinyi@chromium.org, Enric Balletbo i Serra , nancy.lin@mediatek.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Jason: On Mon, 2022-03-07 at 11:28 +0800, jason-jh.lin wrote: > Add mt8195 vdosys0 clock driver name and routing table to > the driver data of mtk-mmsys. > > Signed-off-by: jason-jh.lin > Acked-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > Impelmentation patch of vdosys1 can be refered to [1] > > [1] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 > - > https://patchwork.kernel.org/project/linux-mediatek/patch/20220222100741.30138-6-nancy.lin@mediatek.com/ > --- > drivers/soc/mediatek/mt8195-mmsys.h | 130 > +++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 11 +++ > include/linux/soc/mediatek/mtk-mmsys.h | 9 ++ > 3 files changed, 150 insertions(+) > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h > b/drivers/soc/mediatek/mt8195-mmsys.h > new file mode 100644 > index 000000000000..24a3afe23bc8 > --- /dev/null > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > @@ -0,0 +1,130 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H > +#define __SOC_MEDIATEK_MT8195_MMSYS_H > + > +#define MT8195_VDO0_OVL_MOUT_EN > 0xf14 > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) Useless, so remove. > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) Ditto. Regards, CK > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) > + > +#define MT8195_VDO0_SEL_IN 0xf34 > +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK > (1, 0) > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << > 0) > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << > 0) > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << > 0) > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK > (4, 4) > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << > 4) > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << > 4) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK > (5, 5) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << > 5) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << > 5) > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK > GENMASK(8, 8) > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << > 8) > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT > (1 << 8) > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK > GENMASK(9, 9) > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT > (0 << 9) > +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK > (13, 12) > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << > 0) > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE > (1 << 12) > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << > 12) > +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK > (16, 16) > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT > (0 << 16) > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << > 16) > +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK > (17, 17) > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT > (0 << 17) > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << > 17) > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK > (20, 20) > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 > (0 << 20) > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE > (1 << 20) > +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK > (21, 21) > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN > (0 << 21) > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 > (1 << 21) > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK > (22, 22) > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 > (0 << 22) > + > +#define MT8195_VDO0_SEL_OUT 0xf38 > +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << > 0) > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << > 0) > +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK > (2, 1) > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << > 1) > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE > (1 << 1) > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << > 1) > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK > (4, 4) > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE > (0 << 4) > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 > (1 << 4) > +#define MT8195_SOUT_VPP_MERGE_TO_MASK > GENMASK(10, 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 > (0 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << > 8) > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 > (2 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << > 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN > (4 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK > (11, 11) > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN > (0 << 11) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK > (13, 12) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << > 12) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << > 12) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE > (2 << 12) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK > (17, 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << > 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 > (1 << 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << > 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE > (3 << 16) > + > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = > { > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, > + MT8195_VDO0_OVL_MOUT_EN, > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, > + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 > + }, { > + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, > + MT8195_VDO0_OVL_MOUT_EN, > MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, > + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 > + }, { > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, > + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT > + }, { > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, > + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, > + MT8195_VDO0_SEL_IN, > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 > + }, { > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, > + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, > + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, > + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, > + MT8195_SOUT_DISP_DITHER0_TO_DSI0 > + }, { > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, > + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 > + }, { > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, > + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE > + }, { > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, > + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 > + } > +}; > + > +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ > diff --git a/drivers/soc/mediatek/mtk-mmsys.c > b/drivers/soc/mediatek/mtk-mmsys.c > index 4fc4c2c9ea20..dc5c51f0ccc8 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -17,6 +17,7 @@ > #include "mt8183-mmsys.h" > #include "mt8186-mmsys.h" > #include "mt8192-mmsys.h" > +#include "mt8195-mmsys.h" > #include "mt8365-mmsys.h" > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = > { > @@ -72,6 +73,12 @@ static const struct mtk_mmsys_driver_data > mt8192_mmsys_driver_data = { > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), > }; > > +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data > = { > + .clk_driver = "clk-mt8195-vdo0", > + .routes = mmsys_mt8195_routing_table, > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), > +}; > + > static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = > { > .clk_driver = "clk-mt8365-mm", > .routes = mt8365_mmsys_routing_table, > @@ -260,6 +267,10 @@ static const struct of_device_id > of_match_mtk_mmsys[] = { > .compatible = "mediatek,mt8192-mmsys", > .data = &mt8192_mmsys_driver_data, > }, > + { > + .compatible = "mediatek,mt8195-vdosys0", > + .data = &mt8195_vdosys0_driver_data, > + }, > { > .compatible = "mediatek,mt8365-mmsys", > .data = &mt8365_mmsys_driver_data, > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h > b/include/linux/soc/mediatek/mtk-mmsys.h > index 4bba275e235a..64c77c4a6c56 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -17,13 +17,22 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_COLOR0, > DDP_COMPONENT_COLOR1, > DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DP_INTF0, > DDP_COMPONENT_DPI0, > DDP_COMPONENT_DPI1, > + DDP_COMPONENT_DSC0, > + DDP_COMPONENT_DSC1, > DDP_COMPONENT_DSI0, > DDP_COMPONENT_DSI1, > DDP_COMPONENT_DSI2, > DDP_COMPONENT_DSI3, > DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_MERGE0, > + DDP_COMPONENT_MERGE1, > + DDP_COMPONENT_MERGE2, > + DDP_COMPONENT_MERGE3, > + DDP_COMPONENT_MERGE4, > + DDP_COMPONENT_MERGE5, > DDP_COMPONENT_OD0, > DDP_COMPONENT_OD1, > DDP_COMPONENT_OVL0, _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek