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X-IronPort-AV: E=Sophos;i="5.97,224,1669100400"; d="scan'208";a="196300402" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Jan 2023 01:21:27 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Wed, 18 Jan 2023 01:21:26 -0700 Received: from den-dk-m31857.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Wed, 18 Jan 2023 01:21:07 -0700 Message-ID: <7eb58e2459715a6b2bb5eb45e2ce1f1e88050dff.camel@microchip.com> Subject: Re: [PATCH v2 13/23] arm64: dts: Update cache properties for microchip From: Steen Hegelund To: Pierre Gondois , CC: Rob Herring , Krzysztof Kozlowski , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , "Tsahee Zidenberg" , Antoine Tenart , Brijesh Singh , Suravee Suthikulpanit , Tom Lendacky , "Neil Armstrong" , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Khuong Dinh , Liviu Dudau , "Sudeep Holla" , Lorenzo Pieralisi , William Zhang , Anand Gore , Kursad Oney , =?UTF-8?Q?Rafa=C5=82_Mi=C5=82ecki?= , Alim Akhtar , Shawn Guo , Li Yang , Sascha Hauer , "Pengutronix Kernel Team" , Fabio Estevam , "NXP Linux Team" , Chester Lin , Andreas =?ISO-8859-1?Q?F=E4rber?= , Matthias Brugger , NXP S32 Linux Team , Wei Xu , Chanho Min , Andrew Lunn , Gregory Clement , "Sebastian Hesselbarth" , Lars Povlsen , Daniel Machon , , Avi Fishman , "Tomer Maimon" , Tali Perry , "Patrick Venture" , Nancy Yuen , Benjamin Fair , Thierry Reding , Jonathan Hunter , Andy Gross , "Bjorn Andersson" , Konrad Dybcio , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Kunihiko Hayashi , Masami Hiramatsu , Jisheng Zhang , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Viorel Suman , Abel Vesa , Peng Fan , Ming Qian , Shenwei Wang , Adam Ford , Tim Harvey , Lucas Stach , Richard Zhu , Li Jun , Markus Niebel , Joakim Zhang , Marek Vasut , Laurent Pinchart , Alexander Stein , Paul Elder , Martin Kepplinger , David Heidelberg , "Joy Zou" , Oliver Graute , "Liu Ying" , Zhou Peng , Shijie Qin , Wei Fang , Jacky Bai , Clark Wang , Chris Packham , Vadym Kochan , Sameer Pujar , Akhil R , "Mikko Perttunen" , Prathamesh Shete , Sumit Gupta , Diogo Ivo , Vidya Sagar , Ashish Mhetre , "Johan Jonker" , Christopher Obbard , Ezequiel Garcia , Aswani Reddy , Shashank Prashar , "Arnd Bergmann" , , , , , , , , , , , , Date: Wed, 18 Jan 2023 09:21:07 +0100 In-Reply-To: <20221107155825.1644604-14-pierre.gondois@arm.com> References: <20221107155825.1644604-1-pierre.gondois@arm.com> <20221107155825.1644604-14-pierre.gondois@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.3 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230118_002133_234851_16FF1FFB X-CRM114-Status: GOOD ( 15.47 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Pierre, This looks good to me. Reviewed-by: Steen Hegelund BR Steen On Mon, 2022-11-07 at 16:57 +0100, Pierre Gondois wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know th= e > content is safe >=20 > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > The 'cache-unified' property should be present if one of the > properties for unified cache is present ('cache-size', ...). >=20 > Update the Device Trees accordingly. >=20 > Signed-off-by: Pierre Gondois > --- > =C2=A0arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 + > =C2=A01 file changed, 1 insertion(+) >=20 > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi > b/arch/arm64/boot/dts/microchip/sparx5.dtsi > index 2dd5e38820b1..c4bca23b96b9 100644 > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi > @@ -52,6 +52,7 @@ cpu1: cpu@1 { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 }; > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 L2_0: l2-cache0 { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 compatib= le =3D "cache"; > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cache-level = =3D <2>; > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 }; > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }; >=20 > -- > 2.25.1 >=20