[PATCH 0/4] irqchip/gic: Use GIC_* DT binding definitions

[PATCH 0/4] irqchip/gic: Use GIC_* DT binding definitions

[Geert Uytterhoeven]

	Hi all,

There are still places in GIC DT bindings and GIC-related drivers where
magic GIC and interrupt numbers are used, instead of symbolic
definitions.  This patch series tries to improve upon that.

This series has been tested on a GICv4 system.
The last patch causes no change in generated code.

Noe that the first patch has a contextual conflict with "[PATCH]
irqchip/gic-v3: Print a warning for out-of-range interrupt numbers"[1].

Thanks for your comments!

[1] https://lore.kernel.org/62b849967d71d73e028fb65efee717986ef847e6.1772641758.git.geert+renesas@glider.be

Geert Uytterhoeven (4):
  dt-bindings: interrupt-controller: arm,gic: Document symbolic
    definitions
  genirq: Document interaction between <linux/irq.h> and DT binding defs
  irqchip/gic: Use GIC_* DT binding definitions
  iirqchip/gic children: Use GIC_* DT binding definitions

 .../bindings/interrupt-controller/arm,gic-v3.yaml  | 12 +++++++++---
 .../interrupt-controller/arm,gic-v5-iwb.yaml       |  2 ++
 .../bindings/interrupt-controller/arm,gic-v5.yaml  |  2 ++
 .../bindings/interrupt-controller/arm,gic.yaml     | 11 +++++++++--
 drivers/irqchip/irq-alpine-msi.c                   |  4 +++-
 drivers/irqchip/irq-bcm2712-mip.c                  |  4 +++-
 drivers/irqchip/irq-crossbar.c                     |  8 +++++---
 drivers/irqchip/irq-gic-v2m.c                      |  4 +++-
 drivers/irqchip/irq-gic-v3-mbi.c                   |  6 ++++--
 drivers/irqchip/irq-gic-v3.c                       | 14 ++++++++------
 drivers/irqchip/irq-gic.c                          |  6 ++++--
 drivers/irqchip/irq-imx-gpcv2.c                    |  4 +++-
 drivers/irqchip/irq-meson-gpio.c                   |  4 +++-
 drivers/irqchip/irq-mst-intc.c                     |  6 ++++--
 drivers/irqchip/irq-mtk-cirq.c                     |  4 +++-
 drivers/irqchip/irq-mtk-sysirq.c                   |  6 ++++--
 drivers/irqchip/irq-qcom-mpm.c                     |  4 +++-
 drivers/irqchip/irq-tegra.c                        |  2 +-
 drivers/irqchip/irq-ti-sci-inta.c                  |  4 +++-
 drivers/irqchip/irq-ti-sci-intr.c                  |  4 +++-
 drivers/irqchip/irq-uniphier-aidet.c               |  4 +++-
 drivers/irqchip/qcom-pdc.c                         |  4 +++-
 include/linux/irq.h                                |  4 ++++
 23 files changed, 89 insertions(+), 34 deletions(-)

-- 
2.43.0

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 1/4] dt-bindings: interrupt-controller: arm,gic: Document symbolic definitions

[Geert Uytterhoeven]

Currently, the various GIC DT bindings document the magic GIC and
interrupt numbers used in interrupts properties, but omit any references
to the corresponding symbolic DT binding definitions.

Add references to these symbolic definitions, and convert the examples
to make use of them.  This improves readability, and makes the examples
more similar to what actual users look like.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 .../bindings/interrupt-controller/arm,gic-v3.yaml    | 12 +++++++++---
 .../interrupt-controller/arm,gic-v5-iwb.yaml         |  2 ++
 .../bindings/interrupt-controller/arm,gic-v5.yaml    |  2 ++
 .../bindings/interrupt-controller/arm,gic.yaml       | 11 +++++++++--
 4 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
index 360a0643a0b567a4..d1a4b36f06bc3bdb 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
@@ -46,6 +46,7 @@ properties:
       The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
       interrupts, 2 for interrupts in the Extended SPI range, 3 for the
       Extended PPI range. Other values are reserved for future use.
+      See <dt-bindings/interrupt-controller/arm-gic.h> for symbolic values.
 
       The 2nd cell contains the interrupt number for the interrupt type.
       SPI interrupts are in the range [0-987]. PPI interrupts are in the
@@ -56,6 +57,7 @@ properties:
       bits[3:0] trigger type and level flags.
         1 = edge triggered
         4 = level triggered
+      See <dt-bindings/interrupt-controller/irq.h> for symbolic values.
 
       The 4th cell is a phandle to a node describing a set of CPUs this
       interrupt is affine to. The interrupt must be a PPI, and the node
@@ -237,6 +239,8 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
     gic: interrupt-controller@2cf00000 {
       compatible = "arm,gic-v3";
       #interrupt-cells = <3>;
@@ -249,7 +253,7 @@ examples:
             <0x2c000000 0x2000>,  // GICC
             <0x2c010000 0x2000>,  // GICH
             <0x2c020000 0x2000>;  // GICV
-      interrupts = <1 9 4>;
+      interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
       msi-controller;
       mbi-ranges = <256 128>;
@@ -263,6 +267,8 @@ examples:
     };
 
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
     interrupt-controller@2c010000 {
       compatible = "arm,gic-v3";
       #interrupt-cells = <4>;
@@ -278,7 +284,7 @@ examples:
             <0x2c040000 0x2000>,  // GICC
             <0x2c060000 0x2000>,  // GICH
             <0x2c080000 0x2000>;  // GICV
-      interrupts = <1 9 4 0>;
+      interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 
       msi-controller@2c200000 {
         compatible = "arm,gic-v3-its";
@@ -307,7 +313,7 @@ examples:
 
     device@0 {
       reg = <0 4>;
-      interrupts = <1 1 4 &part0>;
+      interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &part0>;
     };
 
 ...
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb.yaml
index 99a266a62385a354..3103d314fdcae94c 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb.yaml
@@ -46,6 +46,8 @@ properties:
       4 = active high level-sensitive
       8 = active low level-sensitive
 
+      See <dt-bindings/interrupt-controller/irq.h> for symbolic values.
+
     const: 2
 
   interrupt-controller: true
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
index 86ca7f3ac2810312..16c66b043210d815 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
@@ -57,6 +57,8 @@ properties:
         4 = active high level-sensitive
         8 = active low level-sensitive
 
+      See <dt-bindings/interrupt-controller/irq.h> for symbolic values.
+
     const: 3
 
   interrupt-controller: true
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
index ee4c77dac201ad8f..f05917d0071b5446 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
@@ -74,6 +74,7 @@ properties:
     description: |
       The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
       interrupts.
+      See <dt-bindings/interrupt-controller/arm-gic.h> for symbolic values.
 
       The 2nd cell contains the interrupt number for the interrupt type.
       SPI interrupts are in the range [0-987].  PPI interrupts are in the
@@ -85,6 +86,7 @@ properties:
           2 = high-to-low edge triggered (invalid for SPIs)
           4 = active high level-sensitive
           8 = active low level-sensitive (invalid for SPIs).
+        See <dt-bindings/interrupt-controller/irq.h> for symbolic values.
         bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
         the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
         the interrupt is wired to that CPU.  Only valid for PPI interrupts.
@@ -92,6 +94,7 @@ properties:
         DEFINED and as such not guaranteed to be present (most SoC available
         in 2014 seem to ignore the setting of this flag and use the hardware
         default value).
+        See <dt-bindings/interrupt-controller/arm-gic.h> for symbolic values.
 
   reg:
     description: |
@@ -201,6 +204,8 @@ examples:
 
   - |
     // GICv2
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
     interrupt-controller@2c001000 {
       compatible = "arm,cortex-a15-gic";
       #interrupt-cells = <3>;
@@ -209,18 +214,20 @@ examples:
             <0x2c002000 0x2000>,
             <0x2c004000 0x2000>,
             <0x2c006000 0x2000>;
-      interrupts = <1 9 0xf04>;
+      interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
     };
 
   - |
     // GICv2m extension for MSI/MSI-x support
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
     interrupt-controller@e1101000 {
       compatible = "arm,gic-400";
       #interrupt-cells = <3>;
       #address-cells = <1>;
       #size-cells = <1>;
       interrupt-controller;
-      interrupts = <1 8 0xf04>;
+      interrupts = <GIC_PPI 8 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
       ranges = <0 0xe1100000 0x100000>;
       reg = <0xe1110000 0x01000>,
             <0xe112f000 0x02000>,
-- 
2.43.0

[PATCH 2/4] genirq: Document interaction between <linux/irq.h> and DT binding defs

[Geert Uytterhoeven]

Document that the DT binding definitions in
<dt-bindings/interrupt-controller/irq.h> shadow the first six IRQ_TYPE_*
definitions in <linux/irq.h>.  The values must be the same anyway, so
this is harmless (as long as the latter is included first when both are
included), but it is good to document this explicitly.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 include/linux/irq.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 951acbdb9f8457de..efa514ee562fcf91 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -35,6 +35,10 @@ enum irqchip_irq_state;
  *
  * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
  *
+ * Note that the first 6 definitions are shadowed by C preprocessor definitions
+ * in include/dt-bindings/interrupt-controller/irq.h.  This is not an issue, as
+ * the actual values must be the same, due to being part of the stable DT ABI.
+ *
  * IRQ_TYPE_NONE		- default, unspecified type
  * IRQ_TYPE_EDGE_RISING		- rising edge triggered
  * IRQ_TYPE_EDGE_FALLING	- falling edge triggered
-- 
2.43.0

[PATCH 3/4] irqchip/gic: Use GIC_* DT binding definitions

[Geert Uytterhoeven]

Replace magic numbers by symbolic DT binding definitions.  This improves
readability, and makes it easier to find where the various GIC
interrupts types are handled.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/irqchip/irq-gic-v3.c | 14 ++++++++------
 drivers/irqchip/irq-gic.c    |  6 ++++--
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index d75163e71bf22473..6ac103cb40097acc 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -35,6 +35,8 @@
 #include <asm/smp_plat.h>
 #include <asm/virt.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "irq-gic-common.h"
 
 static u8 dist_prio_irq __ro_after_init = GICV3_PRIO_IRQ;
@@ -1602,25 +1604,25 @@ static int gic_irq_domain_translate(struct irq_domain *d,
 			return -EINVAL;
 
 		switch (fwspec->param[0]) {
-		case 0:			/* SPI */
+		case GIC_SPI:
 			if (fwspec->param[1] > 987)
 				pr_warn_once("SPI %u out of range (use ESPI?)\n",
 					     fwspec->param[1]);
 			*hwirq = fwspec->param[1] + 32;
 			break;
-		case 1:			/* PPI */
+		case GIC_PPI:
 			if (fwspec->param[1] > 16)
 				pr_warn_once("PPI %u out of range (use EPPI?)\n",
 					     fwspec->param[1]);
 			*hwirq = fwspec->param[1] + 16;
 			break;
-		case 2:			/* ESPI */
+		case GIC_ESPI:
 			if (fwspec->param[1] > 1023)
 				pr_warn_once("ESPI %u out of range\n",
 					     fwspec->param[1]);
 			*hwirq = fwspec->param[1] + ESPI_BASE_INTID;
 			break;
-		case 3:			/* EPPI */
+		case GIC_EPPI:
 			if (fwspec->param[1] > 63)
 				pr_warn_once("EPPI %u out of range\n",
 					     fwspec->param[1]);
@@ -1738,8 +1740,8 @@ static int gic_irq_get_fwspec_info(struct irq_fwspec *fwspec, struct irq_fwspec_
 		struct fwnode_handle *fw;
 
 		switch (fwspec->param[0]) {
-		case 1:			/* PPI */
-		case 3:			/* EPPI */
+		case GIC_PPI:
+		case GIC_EPPI:
 			break;
 		default:
 			return 0;
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index ec70c84e9f91dd7b..a2225ca1efeb700d 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -47,6 +47,8 @@
 #include <asm/smp_plat.h>
 #include <asm/virt.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "irq-gic-common.h"
 
 #ifdef CONFIG_ARM64
@@ -1094,10 +1096,10 @@ static int gic_irq_domain_translate(struct irq_domain *d,
 			return -EINVAL;
 
 		switch (fwspec->param[0]) {
-		case 0:			/* SPI */
+		case GIC_SPI:
 			*hwirq = fwspec->param[1] + 32;
 			break;
-		case 1:			/* PPI */
+		case GIC_PPI:
 			*hwirq = fwspec->param[1] + 16;
 			break;
 		default:
-- 
2.43.0

[PATCH 4/4] iirqchip/gic children: Use GIC_* DT binding definitions

[Geert Uytterhoeven]

Several interrupt controllers have GICs as their interrupt parents, to
forward SPI interrupts to.  Improve readability by replacing explicit
and implicit magic zeroes by the GIC_SPI constant from the DT binding
definitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/irqchip/irq-alpine-msi.c     | 4 +++-
 drivers/irqchip/irq-bcm2712-mip.c    | 4 +++-
 drivers/irqchip/irq-crossbar.c       | 8 +++++---
 drivers/irqchip/irq-gic-v2m.c        | 4 +++-
 drivers/irqchip/irq-gic-v3-mbi.c     | 6 ++++--
 drivers/irqchip/irq-imx-gpcv2.c      | 4 +++-
 drivers/irqchip/irq-meson-gpio.c     | 4 +++-
 drivers/irqchip/irq-mst-intc.c       | 6 ++++--
 drivers/irqchip/irq-mtk-cirq.c       | 4 +++-
 drivers/irqchip/irq-mtk-sysirq.c     | 6 ++++--
 drivers/irqchip/irq-qcom-mpm.c       | 4 +++-
 drivers/irqchip/irq-tegra.c          | 2 +-
 drivers/irqchip/irq-ti-sci-inta.c    | 4 +++-
 drivers/irqchip/irq-ti-sci-intr.c    | 4 +++-
 drivers/irqchip/irq-uniphier-aidet.c | 4 +++-
 drivers/irqchip/qcom-pdc.c           | 4 +++-
 16 files changed, 51 insertions(+), 21 deletions(-)

diff --git a/drivers/irqchip/irq-alpine-msi.c b/drivers/irqchip/irq-alpine-msi.c
index 6764d64e79500dcb..309b9578ed6de381 100644
--- a/drivers/irqchip/irq-alpine-msi.c
+++ b/drivers/irqchip/irq-alpine-msi.c
@@ -26,6 +26,8 @@
 #include <asm/irq.h>
 #include <asm/msi.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 /* MSIX message address format: local GIC target */
 #define ALPINE_MSIX_SPI_TARGET_CLUSTER0		BIT(16)
 
@@ -89,7 +91,7 @@ static int alpine_msix_gic_domain_alloc(struct irq_domain *domain, unsigned int
 
 	fwspec.fwnode = domain->parent->fwnode;
 	fwspec.param_count = 3;
-	fwspec.param[0] = 0;
+	fwspec.param[0] = GIC_SPI;
 	fwspec.param[1] = sgi;
 	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
 
diff --git a/drivers/irqchip/irq-bcm2712-mip.c b/drivers/irqchip/irq-bcm2712-mip.c
index 06a6ab6270ad36bc..816836f6437c1b26 100644
--- a/drivers/irqchip/irq-bcm2712-mip.c
+++ b/drivers/irqchip/irq-bcm2712-mip.c
@@ -13,6 +13,8 @@
 
 #include <linux/irqchip/irq-msi-lib.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #define MIP_INT_RAISE		0x00
 #define MIP_INT_CLEAR		0x10
 #define MIP_INT_CFGL_HOST	0x20
@@ -99,7 +101,7 @@ static int mip_middle_domain_alloc(struct irq_domain *domain, unsigned int virq,
 
 	fwspec.fwnode = domain->parent->fwnode;
 	fwspec.param_count = 3;
-	fwspec.param[0] = 0;
+	fwspec.param[0] = GIC_SPI;
 	fwspec.param[1] = hwirq + mip->msi_base;
 	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
 
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index cd1134101ace03e3..dc38eed366bf85ea 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -13,6 +13,8 @@
 #include <linux/of_irq.h>
 #include <linux/slab.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #define IRQ_FREE	-1
 #define IRQ_RESERVED	-2
 #define IRQ_SKIP	-3
@@ -95,7 +97,7 @@ static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
 
 	fwspec.fwnode = domain->parent->fwnode;
 	fwspec.param_count = 3;
-	fwspec.param[0] = 0;	/* SPI */
+	fwspec.param[0] = GIC_SPI;
 	fwspec.param[1] = i;
 	fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
 
@@ -117,7 +119,7 @@ static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
 
 	if (fwspec->param_count != 3)
 		return -EINVAL;	/* Not GIC compliant */
-	if (fwspec->param[0] != 0)
+	if (fwspec->param[0] != GIC_SPI)
 		return -EINVAL;	/* No PPI should point to this domain */
 
 	hwirq = fwspec->param[1];
@@ -175,7 +177,7 @@ static int crossbar_domain_translate(struct irq_domain *d,
 			return -EINVAL;
 
 		/* No PPI should point to this domain */
-		if (fwspec->param[0] != 0)
+		if (fwspec->param[0] != GIC_SPI)
 			return -EINVAL;
 
 		*hwirq = fwspec->param[1];
diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c
index bd85bd344f259e19..17311ad7a494016b 100644
--- a/drivers/irqchip/irq-gic-v2m.c
+++ b/drivers/irqchip/irq-gic-v2m.c
@@ -28,6 +28,8 @@
 
 #include <linux/irqchip/irq-msi-lib.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 /*
 * MSI_TYPER:
 *     [31:26] Reserved
@@ -117,7 +119,7 @@ static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
 	if (is_of_node(domain->parent->fwnode)) {
 		fwspec.fwnode = domain->parent->fwnode;
 		fwspec.param_count = 3;
-		fwspec.param[0] = 0;
+		fwspec.param[0] = GIC_SPI;
 		fwspec.param[1] = hwirq - 32;
 		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
 	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-mbi.c
index 62504deb6cd376a4..5a046a92bc52a063 100644
--- a/drivers/irqchip/irq-gic-v3-mbi.c
+++ b/drivers/irqchip/irq-gic-v3-mbi.c
@@ -17,9 +17,11 @@
 #include <linux/spinlock.h>
 
 #include <linux/irqchip/arm-gic-v3.h>
-
 #include <linux/irqchip/irq-msi-lib.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+
 struct mbi_range {
 	u32			spi_start;
 	u32			nr_spis;
@@ -62,7 +64,7 @@ static int mbi_irq_gic_domain_alloc(struct irq_domain *domain,
 	 */
 	fwspec.fwnode = domain->parent->fwnode;
 	fwspec.param_count = 3;
-	fwspec.param[0] = 0;
+	fwspec.param[0] = GIC_SPI;
 	fwspec.param[1] = hwirq - 32;
 	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
 
diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index 6ea10d3356a7ff86..e269ad794c50af96 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -9,6 +9,8 @@
 #include <linux/irqchip.h>
 #include <linux/syscore_ops.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #define IMR_NUM			4
 #define GPC_MAX_IRQS            (IMR_NUM * 32)
 
@@ -151,7 +153,7 @@ static int imx_gpcv2_domain_translate(struct irq_domain *d,
 			return -EINVAL;
 
 		/* No PPI should point to this domain */
-		if (fwspec->param[0] != 0)
+		if (fwspec->param[0] != GIC_SPI)
 			return -EINVAL;
 
 		*hwirq = fwspec->param[1];
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index f722e9c57e2e40a5..9f5849ef5cbf6c44 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -16,6 +16,8 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #define MAX_NUM_CHANNEL 64
 #define MAX_INPUT_MUX 256
 
@@ -488,7 +490,7 @@ static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
 
 	fwspec.fwnode = domain->parent->fwnode;
 	fwspec.param_count = 3;
-	fwspec.param[0] = 0;	/* SPI */
+	fwspec.param[0] = GIC_SPI;
 	fwspec.param[1] = hwirq;
 	fwspec.param[2] = meson_gpio_irq_type_output(type);
 
diff --git a/drivers/irqchip/irq-mst-intc.c b/drivers/irqchip/irq-mst-intc.c
index b5335f6fd6d6e3f6..ca254b2d8cf0a0b5 100644
--- a/drivers/irqchip/irq-mst-intc.c
+++ b/drivers/irqchip/irq-mst-intc.c
@@ -15,6 +15,8 @@
 #include <linux/spinlock.h>
 #include <linux/syscore_ops.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #define MST_INTC_MAX_IRQS	64
 
 #define INTC_MASK		0x0
@@ -189,7 +191,7 @@ static int mst_intc_domain_translate(struct irq_domain *d,
 			return -EINVAL;
 
 		/* No PPI should point to this domain */
-		if (fwspec->param[0] != 0)
+		if (fwspec->param[0] != GIC_SPI)
 			return -EINVAL;
 
 		if (fwspec->param[1] >= cd->nr_irqs)
@@ -216,7 +218,7 @@ static int mst_intc_domain_alloc(struct irq_domain *domain, unsigned int virq,
 		return -EINVAL;
 
 	/* No PPI should point to this domain */
-	if (fwspec->param[0])
+	if (fwspec->param[0] != GIC_SPI)
 		return -EINVAL;
 
 	hwirq = fwspec->param[1];
diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c
index 914d1d639fe303b7..00fb50e8ff40fc1f 100644
--- a/drivers/irqchip/irq-mtk-cirq.c
+++ b/drivers/irqchip/irq-mtk-cirq.c
@@ -15,6 +15,8 @@
 #include <linux/slab.h>
 #include <linux/syscore_ops.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 enum mtk_cirq_regoffs_index {
 	CIRQ_STA,
 	CIRQ_ACK,
@@ -151,7 +153,7 @@ static int mtk_cirq_domain_translate(struct irq_domain *d,
 			return -EINVAL;
 
 		/* No PPI should point to this domain */
-		if (fwspec->param[0] != 0)
+		if (fwspec->param[0] != GIC_SPI)
 			return -EINVAL;
 
 		/* cirq support irq number check */
diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
index 50f88293b4ccf3fe..8259c37710137297 100644
--- a/drivers/irqchip/irq-mtk-sysirq.c
+++ b/drivers/irqchip/irq-mtk-sysirq.c
@@ -14,6 +14,8 @@
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 struct mtk_sysirq_chip_data {
 	raw_spinlock_t lock;
 	u32 nr_intpol_bases;
@@ -78,7 +80,7 @@ static int mtk_sysirq_domain_translate(struct irq_domain *d,
 			return -EINVAL;
 
 		/* No PPI should point to this domain */
-		if (fwspec->param[0] != 0)
+		if (fwspec->param[0] != GIC_SPI)
 			return -EINVAL;
 
 		*hwirq = fwspec->param[1];
@@ -101,7 +103,7 @@ static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 		return -EINVAL;
 
 	/* sysirq doesn't support PPI */
-	if (fwspec->param[0])
+	if (fwspec->param[0] != GIC_SPI)
 		return -EINVAL;
 
 	hwirq = fwspec->param[1];
diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c
index 83f31ea657b74a77..425f7a8914452d12 100644
--- a/drivers/irqchip/irq-qcom-mpm.c
+++ b/drivers/irqchip/irq-qcom-mpm.c
@@ -22,6 +22,8 @@
 #include <linux/soc/qcom/irq.h>
 #include <linux/spinlock.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 /*
  * This is the driver for Qualcomm MPM (MSM Power Manager) interrupt controller,
  * which is commonly found on Qualcomm SoCs built on the RPM architecture.
@@ -247,7 +249,7 @@ static int qcom_mpm_alloc(struct irq_domain *domain, unsigned int virq,
 
 	parent_fwspec.fwnode = domain->parent->fwnode;
 	parent_fwspec.param_count = 3;
-	parent_fwspec.param[0] = 0;
+	parent_fwspec.param[0] = GIC_SPI;
 	parent_fwspec.param[1] = map->hwirq;
 	parent_fwspec.param[2] = type;
 
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
index b449e9cc4034a372..f141f52862796635 100644
--- a/drivers/irqchip/irq-tegra.c
+++ b/drivers/irqchip/irq-tegra.c
@@ -226,7 +226,7 @@ static int tegra_ictlr_domain_translate(struct irq_domain *d,
 			return -EINVAL;
 
 		/* No PPI should point to this domain */
-		if (fwspec->param[0] != 0)
+		if (fwspec->param[0] != GIC_SPI)
 			return -EINVAL;
 
 		*hwirq = fwspec->param[1];
diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci-inta.c
index f1eb2f92f0ca10fd..d2135b304c87adf6 100644
--- a/drivers/irqchip/irq-ti-sci-inta.c
+++ b/drivers/irqchip/irq-ti-sci-inta.c
@@ -23,6 +23,8 @@
 #include <linux/soc/ti/ti_sci_protocol.h>
 #include <asm-generic/msi.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #define TI_SCI_DEV_ID_MASK	0xffff
 #define TI_SCI_DEV_ID_SHIFT	16
 #define TI_SCI_IRQ_ID_MASK	0xffff
@@ -238,7 +240,7 @@ static struct ti_sci_inta_vint_desc *ti_sci_inta_alloc_parent_irq(struct irq_dom
 	if (of_device_is_compatible(parent_node, "arm,gic-v3")) {
 		/* Parent is GIC */
 		parent_fwspec.param_count = 3;
-		parent_fwspec.param[0] = 0;
+		parent_fwspec.param[0] = GIC_SPI;
 		parent_fwspec.param[1] = p_hwirq - 32;
 		parent_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
 	} else {
diff --git a/drivers/irqchip/irq-ti-sci-intr.c b/drivers/irqchip/irq-ti-sci-intr.c
index 0ea17040e934fd0d..8bcc410c3f5aa3ac 100644
--- a/drivers/irqchip/irq-ti-sci-intr.c
+++ b/drivers/irqchip/irq-ti-sci-intr.c
@@ -17,6 +17,8 @@
 #include <linux/platform_device.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 /**
  * struct ti_sci_intr_irq_domain - Structure representing a TISCI based
  *				   Interrupt Router IRQ domain.
@@ -164,7 +166,7 @@ static int ti_sci_intr_alloc_parent_irq(struct irq_domain *domain, unsigned int
 	if (of_device_is_compatible(parent_node, "arm,gic-v3")) {
 		/* Parent is GIC */
 		fwspec.param_count = 3;
-		fwspec.param[0] = 0;	/* SPI */
+		fwspec.param[0] = GIC_SPI;
 		fwspec.param[1] = p_hwirq - 32; /* SPI offset */
 		fwspec.param[2] = hwirq_type;
 	} else {
diff --git a/drivers/irqchip/irq-uniphier-aidet.c b/drivers/irqchip/irq-uniphier-aidet.c
index 6005c2d28dd9389a..bef7978c3d7cd76e 100644
--- a/drivers/irqchip/irq-uniphier-aidet.c
+++ b/drivers/irqchip/irq-uniphier-aidet.c
@@ -16,6 +16,8 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #define UNIPHIER_AIDET_NR_IRQS		256
 
 #define UNIPHIER_AIDET_DETCONF		0x04	/* inverter register base */
@@ -146,7 +148,7 @@ static int uniphier_aidet_domain_alloc(struct irq_domain *domain,
 	/* parent is GIC */
 	parent_fwspec.fwnode = domain->parent->fwnode;
 	parent_fwspec.param_count = 3;
-	parent_fwspec.param[0] = 0;		/* SPI */
+	parent_fwspec.param[0] = GIC_SPI;
 	parent_fwspec.param[1] = hwirq;
 	parent_fwspec.param[2] = type;
 
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 32b77fa93f730416..5340fc9abaec1622 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -20,6 +20,8 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #define PDC_MAX_GPIO_IRQS	256
 #define PDC_DRV_OFFSET		0x10000
 
@@ -295,7 +297,7 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
 
 	parent_fwspec.fwnode      = domain->parent->fwnode;
 	parent_fwspec.param_count = 3;
-	parent_fwspec.param[0]    = 0;
+	parent_fwspec.param[0]    = GIC_SPI;
 	parent_fwspec.param[1]    = pin_to_hwirq(region, hwirq);
 	parent_fwspec.param[2]    = type;
 
-- 
2.43.0

Re: [PATCH 1/4] dt-bindings: interrupt-controller: arm,gic: Document symbolic definitions

[Krzysztof Kozlowski]

On Wed, Mar 04, 2026 at 06:21:56PM +0100, Geert Uytterhoeven wrote:
> Currently, the various GIC DT bindings document the magic GIC and
> interrupt numbers used in interrupts properties, but omit any references
> to the corresponding symbolic DT binding definitions.
> 
> Add references to these symbolic definitions, and convert the examples
> to make use of them.  This improves readability, and makes the examples
> more similar to what actual users look like.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  .../bindings/interrupt-controller/arm,gic-v3.yaml    | 12 +++++++++---
>  .../interrupt-controller/arm,gic-v5-iwb.yaml         |  2 ++
>  .../bindings/interrupt-controller/arm,gic-v5.yaml    |  2 ++
>  .../bindings/interrupt-controller/arm,gic.yaml       | 11 +++++++++--
>  4 files changed, 22 insertions(+), 5 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 3/4] irqchip/gic: Use GIC_* DT binding definitions

[Marc Zyngier]

On Wed, 04 Mar 2026 17:21:58 +0000,
Geert Uytterhoeven <geert+renesas@glider.be> wrote:
> 
> Replace magic numbers by symbolic DT binding definitions.  This improves
> readability, and makes it easier to find where the various GIC
> interrupts types are handled.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/irqchip/irq-gic-v3.c | 14 ++++++++------
>  drivers/irqchip/irq-gic.c    |  6 ++++--
>  2 files changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index d75163e71bf22473..6ac103cb40097acc 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -35,6 +35,8 @@
>  #include <asm/smp_plat.h>
>  #include <asm/virt.h>
>  
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
>  #include "irq-gic-common.h"
>  
>  static u8 dist_prio_irq __ro_after_init = GICV3_PRIO_IRQ;
> @@ -1602,25 +1604,25 @@ static int gic_irq_domain_translate(struct irq_domain *d,
>  			return -EINVAL;
>  
>  		switch (fwspec->param[0]) {
> -		case 0:			/* SPI */
> +		case GIC_SPI:

I'd rather not do that. I use *numeric* values on purpose, because
that's what the DT *binding* describes, and I have no control over
what lives in that include file (it gets changed without me being even
Cc'd).

So I want to stick to the binding, and not to the interpretation of
it. If you want symbolic values to be used, describe them in the
binding, have a tool to generate the values from the binding, and use
that everywhere.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH 3/4] irqchip/gic: Use GIC_* DT binding definitions

[Geert Uytterhoeven]

Hi Marc,

On Thu, 5 Mar 2026 at 11:13, Marc Zyngier <maz@kernel.org> wrote:
> On Wed, 04 Mar 2026 17:21:58 +0000,
> Geert Uytterhoeven <geert+renesas@glider.be> wrote:
> > Replace magic numbers by symbolic DT binding definitions.  This improves
> > readability, and makes it easier to find where the various GIC
> > interrupts types are handled.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

> > --- a/drivers/irqchip/irq-gic-v3.c
> > +++ b/drivers/irqchip/irq-gic-v3.c
> > @@ -35,6 +35,8 @@
> >  #include <asm/smp_plat.h>
> >  #include <asm/virt.h>
> >
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> >  #include "irq-gic-common.h"
> >
> >  static u8 dist_prio_irq __ro_after_init = GICV3_PRIO_IRQ;
> > @@ -1602,25 +1604,25 @@ static int gic_irq_domain_translate(struct irq_domain *d,
> >                       return -EINVAL;
> >
> >               switch (fwspec->param[0]) {
> > -             case 0:                 /* SPI */
> > +             case GIC_SPI:
>
> I'd rather not do that. I use *numeric* values on purpose, because
> that's what the DT *binding* describes, and I have no control over
> what lives in that include file (it gets changed without me being even
> Cc'd).
>
> So I want to stick to the binding, and not to the interpretation of
> it. If you want symbolic values to be used, describe them in the
> binding, have a tool to generate the values from the binding, and use
> that everywhere.

This sounds more like a philosophical debate, so I'd like to defer
to the DT maintainers...

About you not being notified: that can be fixed easily ;-)

--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2110,6 +2110,7 @@ F:        arch/arm64/include/asm/arch_gicv3.h
 F:     drivers/irqchip/irq-gic*.[ch]
 F:     include/linux/irqchip/arm-gic*.h
 F:     include/linux/irqchip/arm-vgic-info.h
+F:     include/dt-bindings/interrupt-controller/arm-gic.h

 ARM GENERIC INTERRUPT CONTROLLER V5 DRIVERS
 M:     Lorenzo Pieralisi <lpieralisi@kernel.org>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/4] irqchip/gic: Use GIC_* DT binding definitions

[Marc Zyngier]

On Thu, 05 Mar 2026 10:24:23 +0000,
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> 
> Hi Marc,
> 
> On Thu, 5 Mar 2026 at 11:13, Marc Zyngier <maz@kernel.org> wrote:
> > On Wed, 04 Mar 2026 17:21:58 +0000,
> > Geert Uytterhoeven <geert+renesas@glider.be> wrote:
> > > Replace magic numbers by symbolic DT binding definitions.  This improves
> > > readability, and makes it easier to find where the various GIC
> > > interrupts types are handled.
> > >
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> > > --- a/drivers/irqchip/irq-gic-v3.c
> > > +++ b/drivers/irqchip/irq-gic-v3.c
> > > @@ -35,6 +35,8 @@
> > >  #include <asm/smp_plat.h>
> > >  #include <asm/virt.h>
> > >
> > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > >  #include "irq-gic-common.h"
> > >
> > >  static u8 dist_prio_irq __ro_after_init = GICV3_PRIO_IRQ;
> > > @@ -1602,25 +1604,25 @@ static int gic_irq_domain_translate(struct irq_domain *d,
> > >                       return -EINVAL;
> > >
> > >               switch (fwspec->param[0]) {
> > > -             case 0:                 /* SPI */
> > > +             case GIC_SPI:
> >
> > I'd rather not do that. I use *numeric* values on purpose, because
> > that's what the DT *binding* describes, and I have no control over
> > what lives in that include file (it gets changed without me being even
> > Cc'd).
> >
> > So I want to stick to the binding, and not to the interpretation of
> > it. If you want symbolic values to be used, describe them in the
> > binding, have a tool to generate the values from the binding, and use
> > that everywhere.
> 
> This sounds more like a philosophical debate, so I'd like to defer
> to the DT maintainers...

That's not philosophical.

That's a pragmatic approach to having a common source of information,
and a unique reference. Carrying an extra copy that can be
independently changed is a source of errors, which I've been trying to
reduce in other parts of the kernel (system register description and
encoding, for example).

> 
> About you not being notified: that can be fixed easily ;-)
> 
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2110,6 +2110,7 @@ F:        arch/arm64/include/asm/arch_gicv3.h
>  F:     drivers/irqchip/irq-gic*.[ch]
>  F:     include/linux/irqchip/arm-gic*.h
>  F:     include/linux/irqchip/arm-vgic-info.h
> +F:     include/dt-bindings/interrupt-controller/arm-gic.h

I'm actively trying to *remove* myself from the kernel, not to grab
more stuff.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.