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From: Esben Haabendal <esben@geanix.com>
To: "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>
Cc: "Gary Bisson" <bisson.gary@gmail.com>,
	 "Chun-Kuang Hu" <chunkuang.hu@kernel.org>,
	 "Philipp Zabel" <p.zabel@pengutronix.de>,
	"David Airlie" <airlied@gmail.com>,
	 "Simona Vetter" <simona@ffwll.ch>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	<dri-devel@lists.freedesktop.org>,
	 <linux-mediatek@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	 <linux-arm-kernel@lists.infradead.org>,
	"Adam Thiede" <me@adamthiede.com>,
	 "Thorsten Leemhuis" <regressions@leemhuis.info>
Subject: Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable
Date: Wed, 15 Jul 2026 15:52:05 +0200	[thread overview]
Message-ID: <87h5m0mkca.fsf@geanix.com> (raw)
In-Reply-To: <65558ccc-4f2c-492d-8c74-627d27dce864@collabora.com> (AngeloGioacchino Del Regno's message of "Wed, 15 Jul 2026 15:40:37 +0200")

"AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>
writes:

> On 7/15/26 15:36, Gary Bisson wrote:
>> Hi,
>>
>> On Wed, Jul 15, 2026 at 03:25:11PM +0200, AngeloGioacchino Del Regno wrote:
>>> On 7/15/26 14:53, Esben Haabendal wrote:
>>>> Gary Bisson <bisson.gary@gmail.com> writes:
>>>>
>>>>> Some bridges, such as the TI SN65DSI83, require the HS clock to be
>>>>> running in order to lock its PLL during its own pre-enable function.
>>>>>
>>>>> Without this change, the bridge gives the following error:
>>>>> sn65dsi83 14-002c: failed to lock PLL, ret=-110
>>>>> sn65dsi83 14-002c: Unexpected link status 0x01
>>>>> sn65dsi83 14-002c: reset the pipe
>>>>>
>>>>> Move the necessary functions from enable to pre-enable.
>>>>>
>>>>> Signed-off-by: Gary Bisson <bisson.gary@gmail.com>
>>>>
>>>> Hi
>>>>
>>>> I have run into the same problem, but in combination with another
>>>> pipeline. I am seeing same problem with an i.MX8 using the nwl-dsi
>>>> bridge and the dcss driver.
>>>>
>>>> I have submitted a fix that adresses the problem in the ti-sn65dsi83
>>>> driver instead. With a bit of luck, it can replace the fix proposed in
>>>> this thread.
>>>>
>>>> See https://lore.kernel.org/all/20260711-ti-sn65dsi83-fixes-v1-2-d85eb5342b98@geanix.com/
>>
>> Thanks, just tried it on 7.2-rc3 with my patch reverted and confirm that
>> it works too. My assumption was that the SN65DSI83 was locking the PLL
>> earlier for some specific reason and therefore was reluctant to change
>> it.
>>
>>>> /Esben
>>>
>>> That clarifies a lot of things.
>>>
>>> The patch on mtk_dsi shall be reverted then.
>>
>> Angelo, do you want me to offer the revert patch? Should I wait to see
>> how the other thread goes?
>>
>
> Gary, yes please, send a revert and make sure to explain the reason why
> we're reverting this in the commit description :-)

Maybe test if my fix actually solves the problem with the mtk_dsi driver
also ;)

/Esben


      reply	other threads:[~2026-07-15 13:52 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-20 11:36 [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable Gary Bisson
2026-02-25  6:20 ` CK Hu (胡俊光)
2026-02-25  8:20   ` Chen-Yu Tsai
2026-02-25 13:16   ` AngeloGioacchino Del Regno
2026-03-22 12:48 ` Chun-Kuang Hu
2026-06-18 21:06 ` Adam Thiede
2026-06-22 11:22   ` Gary Bisson
2026-06-22 13:23     ` Adam Thiede
2026-07-06 10:16       ` Thorsten Leemhuis
2026-07-07  2:20         ` CK Hu (胡俊光)
2026-07-07  8:51           ` Thorsten Leemhuis
2026-07-07 10:38             ` AngeloGioacchino Del Regno
2026-07-08  1:25               ` Adam Thiede
2026-07-08 12:12                 ` AngeloGioacchino Del Regno
2026-07-08 12:13                 ` Gary Bisson
2026-07-08 12:25                   ` AngeloGioacchino Del Regno
2026-07-15 12:53 ` Esben Haabendal
2026-07-15 13:25   ` AngeloGioacchino Del Regno
2026-07-15 13:36     ` Gary Bisson
2026-07-15 13:40       ` AngeloGioacchino Del Regno
2026-07-15 13:52         ` Esben Haabendal [this message]

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