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From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Laura Nao <laura.nao@collabora.com>,
	mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
	p.zabel@pengutronix.de, richardcochran@gmail.com
Cc: guangjie.song@mediatek.com, wenst@chromium.org,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
	kernel@collabora.com
Subject: Re: [PATCH 00/30] Add support for MT8196 clock controllers
Date: Mon, 23 Jun 2025 13:34:55 +0200	[thread overview]
Message-ID: <88a04bcc-b287-432c-b309-5c76259ceda3@collabora.com> (raw)
In-Reply-To: <20250623102940.214269-1-laura.nao@collabora.com>

Il 23/06/25 12:29, Laura Nao ha scritto:
> This patch series introduces support for the clock controllers on the
> MediaTek MT8196 platform, following up on an earlier submission[1].
> 
> MT8196 uses a hardware voting mechanism to control some of the clock muxes
> and gates, along with a fence register responsible for tracking PLL and mux
> gate readiness. The series introduces support for these voting and fence
> mechanisms, and includes drivers for all clock controllers on the platform.
> 

Whole series is

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

(as I reviewed this entire thing internally and before submission anyway :-D)

Cheers,
Angelo


> [1] https://lore.kernel.org/all/20250307032942.10447-1-guangjie.song@mediatek.com/
> 
> AngeloGioacchino Del Regno (2):
>    dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding
>    clk: mediatek: mt8196: Add UFS and PEXTP0/1 reset controllers
> 
> Laura Nao (28):
>    clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control
>    clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC
>    clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and
>      FENC
>    clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()
>    clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC
>    clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use
>      mtk_gate struct
>    clk: mediatek: clk-gate: Add ops for gates with HW voter
>    clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
>    dt-bindings: clock: mediatek: Describe MT8196 peripheral clock
>      controllers
>    clk: mediatek: Add MT8196 apmixedsys clock support
>    clk: mediatek: Add MT8196 topckgen clock support
>    clk: mediatek: Add MT8196 topckgen2 clock support
>    clk: mediatek: Add MT8196 vlpckgen clock support
>    clk: mediatek: Add MT8196 peripheral clock support
>    clk: mediatek: Add MT8196 ufssys clock support
>    clk: mediatek: Add MT8196 pextpsys clock support
>    clk: mediatek: Add MT8196 adsp clock support
>    clk: mediatek: Add MT8196 I2C clock support
>    clk: mediatek: Add MT8196 mcu clock support
>    clk: mediatek: Add MT8196 mdpsys clock support
>    clk: mediatek: Add MT8196 mfg clock support
>    clk: mediatek: Add MT8196 disp0 clock support
>    clk: mediatek: Add MT8196 disp1 clock support
>    clk: mediatek: Add MT8196 disp-ao clock support
>    clk: mediatek: Add MT8196 ovl0 clock support
>    clk: mediatek: Add MT8196 ovl1 clock support
>    clk: mediatek: Add MT8196 vdecsys clock support
>    clk: mediatek: Add MT8196 vencsys clock support
> 
>   .../bindings/clock/mediatek,mt8196-clock.yaml |   79 ++
>   .../clock/mediatek,mt8196-sys-clock.yaml      |   76 +
>   drivers/clk/mediatek/Kconfig                  |   78 +
>   drivers/clk/mediatek/Makefile                 |   14 +
>   drivers/clk/mediatek/clk-gate.c               |  106 +-
>   drivers/clk/mediatek/clk-gate.h               |    3 +
>   drivers/clk/mediatek/clk-mt8196-adsp.c        |  193 +++
>   drivers/clk/mediatek/clk-mt8196-apmixedsys.c  |  203 +++
>   drivers/clk/mediatek/clk-mt8196-disp0.c       |  169 +++
>   drivers/clk/mediatek/clk-mt8196-disp1.c       |  170 +++
>   .../clk/mediatek/clk-mt8196-imp_iic_wrap.c    |  117 ++
>   drivers/clk/mediatek/clk-mt8196-mcu.c         |  166 +++
>   drivers/clk/mediatek/clk-mt8196-mdpsys.c      |  187 +++
>   drivers/clk/mediatek/clk-mt8196-mfg.c         |  150 ++
>   drivers/clk/mediatek/clk-mt8196-ovl0.c        |  154 ++
>   drivers/clk/mediatek/clk-mt8196-ovl1.c        |  153 ++
>   drivers/clk/mediatek/clk-mt8196-peri_ao.c     |  144 ++
>   drivers/clk/mediatek/clk-mt8196-pextp.c       |  131 ++
>   drivers/clk/mediatek/clk-mt8196-topckgen.c    | 1257 +++++++++++++++++
>   drivers/clk/mediatek/clk-mt8196-topckgen2.c   |  662 +++++++++
>   drivers/clk/mediatek/clk-mt8196-ufs_ao.c      |  109 ++
>   drivers/clk/mediatek/clk-mt8196-vdec.c        |  253 ++++
>   drivers/clk/mediatek/clk-mt8196-vdisp_ao.c    |   78 +
>   drivers/clk/mediatek/clk-mt8196-venc.c        |  235 +++
>   drivers/clk/mediatek/clk-mt8196-vlpckgen.c    |  769 ++++++++++
>   drivers/clk/mediatek/clk-mtk.c                |   16 +
>   drivers/clk/mediatek/clk-mtk.h                |   23 +
>   drivers/clk/mediatek/clk-mux.c                |  119 +-
>   drivers/clk/mediatek/clk-mux.h                |   76 +
>   drivers/clk/mediatek/clk-pll.c                |   46 +-
>   drivers/clk/mediatek/clk-pll.h                |    9 +
>   .../dt-bindings/clock/mediatek,mt8196-clock.h |  867 ++++++++++++
>   .../reset/mediatek,mt8196-resets.h            |   26 +
>   33 files changed, 6814 insertions(+), 24 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml
>   create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-adsp.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-apmixedsys.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-disp0.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-disp1.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-mcu.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-mdpsys.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-mfg.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl0.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-ovl1.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-peri_ao.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-pextp.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen2.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-ufs_ao.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-vdec.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-venc.c
>   create mode 100644 drivers/clk/mediatek/clk-mt8196-vlpckgen.c
>   create mode 100644 include/dt-bindings/clock/mediatek,mt8196-clock.h
>   create mode 100644 include/dt-bindings/reset/mediatek,mt8196-resets.h
> 



      parent reply	other threads:[~2025-06-23 13:14 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-23 10:29 [PATCH 00/30] Add support for MT8196 clock controllers Laura Nao
2025-06-23 10:29 ` [PATCH 01/30] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-06-23 10:29 ` [PATCH 02/30] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-06-23 10:29 ` [PATCH 03/30] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-06-23 10:29 ` [PATCH 04/30] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-06-23 10:29 ` [PATCH 05/30] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-06-23 10:29 ` [PATCH 06/30] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-06-23 10:29 ` [PATCH 07/30] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-06-23 10:29 ` [PATCH 08/30] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-06-23 10:29 ` [PATCH 09/30] dt-bindings: clock: mediatek: Describe MT8196 peripheral clock controllers Laura Nao
2025-06-23 12:12   ` Krzysztof Kozlowski
2025-06-23 12:28     ` AngeloGioacchino Del Regno
2025-06-23 10:29 ` [PATCH 10/30] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-06-23 10:29 ` [PATCH 11/30] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-06-23 10:29 ` [PATCH 12/30] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-06-23 10:29 ` [PATCH 13/30] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-06-23 10:29 ` [PATCH 14/30] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-06-23 10:29 ` [PATCH 15/30] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-06-23 10:29 ` [PATCH 16/30] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-06-23 10:29 ` [PATCH 17/30] clk: mediatek: Add MT8196 adsp " Laura Nao
2025-06-23 10:29 ` [PATCH 18/30] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-06-23 10:29 ` [PATCH 19/30] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-06-23 10:29 ` [PATCH 20/30] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-06-23 10:29 ` [PATCH 21/30] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-06-23 10:29 ` [PATCH 22/30] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-06-23 10:29 ` [PATCH 23/30] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-06-23 10:29 ` [PATCH 24/30] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-06-24  6:40   ` kernel test robot
2025-06-23 10:29 ` [PATCH 25/30] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-06-23 10:29 ` [PATCH 26/30] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-06-23 10:29 ` [PATCH 27/30] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-06-23 10:29 ` [PATCH 28/30] clk: mediatek: Add MT8196 vencsys " Laura Nao
2025-06-23 10:29 ` [PATCH 29/30] dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding Laura Nao
2025-06-23 12:13   ` Krzysztof Kozlowski
2025-06-23 12:22     ` AngeloGioacchino Del Regno
2025-06-23 10:29 ` [PATCH 30/30] clk: mediatek: mt8196: Add UFS and PEXTP0/1 reset controllers Laura Nao
2025-06-23 12:14   ` Krzysztof Kozlowski
2025-06-23 12:33     ` AngeloGioacchino Del Regno
2025-06-23 11:34 ` AngeloGioacchino Del Regno [this message]

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