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Thu, 03 Oct 2024 01:57:53 -0700 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 3 Oct 2024 16:57:51 +0800 Received: from [172.21.84.99] (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 3 Oct 2024 16:57:50 +0800 Message-ID: <8b428ac5-2bd9-47cf-1dc4-7594c1b05b94@mediatek.com> Date: Thu, 3 Oct 2024 16:57:48 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v2 2/9] arm64: dts: mediatek: mt8188: Add PCIe nodes Content-Language: en-US To: Fei Shao , AngeloGioacchino Del Regno , Matthias Brugger , Jieyy Yang , Jianguo Zhang , Jian Yang CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , , , , References: <20241003070139.1461472-1-fshao@chromium.org> <20241003070139.1461472-3-fshao@chromium.org> From: Macpaul Lin In-Reply-To: <20241003070139.1461472-3-fshao@chromium.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241003_015758_455469_D9B0E17A X-CRM114-Status: GOOD ( 16.40 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On 10/3/24 14:59, Fei Shao wrote: > > > External email : Please do not click links or open attachments until you > have verified the sender or the content. > > > Add PCIe node and the associated PHY node. > Individual board device tree should enable the nodes as needed. > > Signed-off-by: Fei Shao > --- > > Changes in v2: > - add linux,pci-domain to PCIe node > - add power domain to PCIe PHY node. > The binding patch: > https://lore.kernel.org/all/20240926101804.22471-1-macpaul.lin@mediatek.com/ > > arch/arm64/boot/dts/mediatek/mt8188.dtsi | 64 ++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi > index 10195a4e4e9d..23101d316c4e 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi > @@ -1763,6 +1763,54 @@ xhci0: usb@112b0000 { > status = "disabled"; > }; > > + pcie: pcie@112f0000 { > + compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; > + reg = <0 0x112f0000 0 0x2000>; > + reg-names = "pcie-mac"; > + ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; > + bus-range = <0 0xff>; > + device_type = "pci"; > + linux,pci-domain = <0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, > + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, > + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, > + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, > + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, > + <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; > + clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", > + "peri_26m", "peri_mem"; > + > + #interrupt-cells = <1>; > + interrupts = ; > + interrupt-map = <0 0 0 1 &pcie_intc 0>, > + <0 0 0 2 &pcie_intc 1>, > + <0 0 0 3 &pcie_intc 2>, > + <0 0 0 4 &pcie_intc 3>; > + interrupt-map-mask = <0 0 0 7>; > + > + iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; > + iommu-map-mask = <0>; > + > + phys = <&pcieport PHY_TYPE_PCIE>; > + phy-names = "pcie-phy"; > + > + power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; > + > + resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; > + reset-names = "mac"; > + > + status = "disabled"; > + > + pcie_intc: interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + }; > + > nor_flash: spi@1132c000 { > compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; > reg = <0 0x1132c000 0 0x1000>; > @@ -1775,6 +1823,22 @@ nor_flash: spi@1132c000 { > status = "disabled"; > }; > > + pciephy: t-phy@11c20700 { > + compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; > + ranges = <0 0 0x11c20700 0x700>; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; > + status = "disabled"; > + > + pcieport: pcie-phy@0 { > + reg = <0 0x700>; > + clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; > + clock-names = "ref"; > + #phy-cells = <1>; > + }; > + }; > + > i2c1: i2c@11e00000 { > compatible = "mediatek,mt8188-i2c"; > reg = <0 0x11e00000 0 0x1000>, Reviewed-by: Macpaul Lin Thanks. Macpaul Lin