Re: [PATCH 2/2] drm/mediatek: dp: Add the audio control to mtk_dp_data struct

["Rex-BC Chen (陳柏辰)" <Rex-BC.Chen@mediatek.com>]

Hello Xinlei,

My comments below:

On Thu, 2023-04-13 at 12:06 +0800, xinlei.lee@mediatek.com wrote:
> From: Xinlei Lee <xinlei.lee@mediatek.com>
> 
> Mainly add the following two flag:
> 
> 1.The audio packet arrangement function is to only arrange audio
> packets into the Hblanking area. In order to align with the HW
> default setting of g1200, this function needs to be turned off.
> 

what is g1200?

> 2.Due to the difference of HW, different dividers need to be set.
> 
> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dp.c     | 32
> ++++++++++++++++++++++++++-
>  drivers/gpu/drm/mediatek/mtk_dp_reg.h |  5 +++++
>  2 files changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
> b/drivers/gpu/drm/mediatek/mtk_dp.c
> index 767b71da31a4..65a9984eac81 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -139,6 +139,8 @@ struct mtk_dp_data {
>  	unsigned int smc_cmd;
>  	const struct mtk_dp_efuse_fmt *efuse_fmt;
>  	bool audio_supported;
> +	const bool arrange;
> +	const u8 audio_m_div2;
>  };
>  
>  static const struct mtk_dp_efuse_fmt
> mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {
> @@ -646,8 +648,10 @@ static void
> mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp,
>  
>  static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp)
>  {
> +	u8 div2_id = mtk_dp->data->audio_m_div2;
> +
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC,
> -			   AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
> +			   div2_id <<
> AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT,
>  			   AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);
>  }
>  
> @@ -1362,6 +1366,14 @@ static void
> mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp)
>  			   SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK)
> ;
>  }
>  
> +static void mtk_dp_audio_sample_arrange(struct mtk_dp *mtk_dp)
> +{
> +	if (mtk_dp->data->arrange) {
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,
> BIT(12));
> +		mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,
> 0xFFF);
> +	}
> +}
> +

Remove "if (mtk_dp->data->arrange)" and add them ouside this function.

>  static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)
>  {
>  	u32 sram_read_start = min_t(u32,
> MTK_DP_TBC_BUF_READ_START_ADDR,
> @@ -1371,6 +1383,7 @@ static void mtk_dp_setup_tu(struct mtk_dp
> *mtk_dp)
>  				    MTK_DP_PIX_PER_ADDR);
>  	mtk_dp_set_sram_read_start(mtk_dp, sram_read_start);
>  	mtk_dp_setup_encoder(mtk_dp);
> +	mtk_dp_audio_sample_arrange(mtk_dp);

if (mtk_dp->data->arrange)
        mtk_dp_audio_sample_arrange(mtk_dp);


BRs,
Bo-Chen

>  	mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp);
>  	mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start);
>  }
> @@ -2615,11 +2628,22 @@ static int mtk_dp_resume(struct device *dev)
>  
>  static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend,
> mtk_dp_resume);
>  
> +static const struct mtk_dp_data mt8188_dp_data = {
> +	.bridge_type = DRM_MODE_CONNECTOR_DisplayPort,
> +	.smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
> +	.efuse_fmt = mt8195_dp_efuse_fmt,
> +	.audio_supported = true,
> +	.arrange = true,
> +	.audio_m_div2 = 4,
> +};
> +
>  static const struct mtk_dp_data mt8195_edp_data = {
>  	.bridge_type = DRM_MODE_CONNECTOR_eDP,
>  	.smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,
>  	.efuse_fmt = mt8195_edp_efuse_fmt,
>  	.audio_supported = false,
> +	.arrange = false,
> +	.audio_m_div2 = 5,
>  };
>  
>  static const struct mtk_dp_data mt8195_dp_data = {
> @@ -2627,9 +2651,15 @@ static const struct mtk_dp_data mt8195_dp_data
> = {
>  	.smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
>  	.efuse_fmt = mt8195_dp_efuse_fmt,
>  	.audio_supported = true,
> +	.arrange = false,
> +	.audio_m_div2 = 5,
>  };
>  
>  static const struct of_device_id mtk_dp_of_match[] = {
> +	{
> +		.compatible = "mediatek,mt8188-dp-tx",
> +		.data = &mt8188_dp_data,
> +	},
>  	{
>  		.compatible = "mediatek,mt8195-edp-tx",
>  		.data = &mt8195_edp_data,
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> index 84e38cef03c2..4dc4f7cd0ef2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> @@ -158,6 +158,7 @@
>  #define MTK_DP_ENC0_P0_30A8			0x30a8
>  #define MTK_DP_ENC0_P0_30BC			0x30bc
>  #define ISRC_CONT_DP_ENC0_P0				BIT(0)
> +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT	8
>  #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK	GENMASK(10, 8)
>  #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2	(1 << 8)
>  #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4	(2 << 8)
> @@ -228,6 +229,10 @@
>  							 VIDEO_STABLE_C
> NT_THRD_DP_ENC1_P0 | \
>  							 SDP_DP13_EN_DP
> _ENC1_P0 | \
>  							 BS2BS_MODE_DP_
> ENC1_P0)
> +
> +#define MTK_DP_ENC1_P0_3374			0x3374
> +#define AU_ASP_PACKET_ONLY_IN_HBLANK_ENABLE_MASK	0x1000
> +
>  #define MTK_DP_ENC1_P0_33F4			0x33f4
>  #define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN			BIT(0)
>  #define DP_ENC_DUMMY_RW_1				BIT(9)