Re: [PATCH 2/2] phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting

[AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>]

On 9/11/26 07:11, Manivannan Sadhasivam wrote:
> On Thu, Sep 10, 2026 at 10:39:06AM +0200, AngeloGioacchino Del Regno wrote:
>> On 9/9/26 17:06, Manivannan Sadhasivam wrote:
>>> On Wed, Jul 01, 2026 at 02:19:36PM +0200, AngeloGioacchino Del Regno wrote:
>>>> The comment in the mtk_phy_tmds_clk_ratio() function clearly and
>>>> correctly explains that the TMDS ratio has to be 1/10 for data
>>>> rates under 3.4Gbps, and 1/40 over that.
>>>>
>>>> Unfortunately though, the TXC_DIV register setting was wrong, as
>>>> in value 3 means to divide by 8 and, in order to achieve the in
>>>> spec 1/40 (tmds) data rate, this has to divide by 4 instead!
>>>> In order to achieve the correct 1/40 (tmds) data rate, this has
>>>
>>> This statement is cut-off!
>>>
>>
>> Oh oops. It's just a forgotten line that has to be removed....
>>
>> Should I resend or can you simply remove the line
>> "In order to achieve the correct 1/40 (tmds) data rate, this has"
>> while applying?
>>
> 
> I do not apply the patches, only Vinod does. It would help if you can just
> send a next version with this change and tags.
> 
> - Mani
> 

Sure, will send v2 in a jiffy.

Cheers,
Angelo