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Tue, 16 Apr 2024 07:53:09 -0700 (PDT) Received: from [192.168.1.172] ([93.5.22.158]) by smtp.gmail.com with ESMTPSA id c19-20020a170906529300b00a4da28f42f1sm6995974ejm.177.2024.04.16.07.53.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Apr 2024 07:53:08 -0700 (PDT) Message-ID: <96d90ddd-2910-4419-ba90-64a09a3dbf1e@baylibre.com> Date: Tue, 16 Apr 2024 16:53:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Alexandre Mergnat Subject: Re: [PATCH 14/18] drm/mediatek: dpi: add support for dpi clock To: AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, Krzysztof Kozlowski , Matthias Brugger , linux-mediatek@lists.infradead.org, Will Deacon , Catalin Marinas , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, CK Hu , Rob Herring , Daniel Vetter , David Airlie , Xinlei Lee , Jitao Shi , linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Conor Dooley , Thierry Reding , Fabien Parent , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Chun-Kuang Hu , Philipp Zabel References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> <20231023-display-support-v1-14-5c860ed5c33b@baylibre.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240416_075315_758566_8ADB6925 X-CRM114-Status: GOOD ( 17.58 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On 24/10/2023 11:12, AngeloGioacchino Del Regno wrote: > Il 23/10/23 16:40, amergnat@baylibre.com ha scritto: >> From: Fabien Parent >> >> MT8365 requires an additional clock for DPI. Add support for that >> additional clock. >> >> Signed-off-by: Fabien Parent >> Signed-off-by: Alexandre Mergnat > > I'm not convinced that this is right... at all. > > From a fast check of the MT8365 DPI clocks, I can see that the DPI0 > clock declares > parent VPLL_DPIX (a fixed clock), but nothing ever has VPLL_DPIX_EN > (which is the > GATE clock, enabling output of DPIx VPLL?). > > But then, there's even more: no clock ever references the > CLK_TOP_DPI0_SEL nor the > CLK_TOP_DPI1_SEL gate, which is a PLL parent selector... in other > platforms, that > is muxing through the TVDPLL, but on MT8365 that is LVDSPLL?! AFAI see into mt8365 documentation, there is no TVDPLL, only LVDSPLL > > I have many questions now: > * Two PLLs are apparently brought up, but which one is the right one?! >   * Is the LVDS PLL really used for DisplayPort? (dpi0_sel) Seems to be LVDS enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- clk26m 18 19 1 26000000 0 0 Y vpll_dpix 1 1 0 75000000 0 0 50000 Y mm_flvdstx_pxl 0 0 0 75000000 0 0 50000 N mm_dpi0_dpi0 1 1 0 75000000 0 0 50000 Y vpll_dpix_en 0 0 0 75000000 0 0 50000 N lvdspll 1 1 0 283999497 0 0 50000 Y lvdspll_d16 0 0 0 17749968 0 0 50000 Y lvdspll_d8 0 0 0 35499937 0 0 50000 Y lvdspll_d4 0 0 0 70999874 0 0 50000 Y lvdspll_d2 1 1 0 141999748 0 0 50000 Y dpi0_sel 1 1 0 141999748 0 0 50000 Y dpi1_sel 0 0 0 141999748 0 0 50000 N mmpll 1 1 0 456999909 0 0 50000 Y mmpll_ck 1 1 0 456999909 0 0 50000 Y mm_sel 15 15 0 456999909 0 0 50000 Y mm_dpi0 1 1 0 456999909 0 0 50000 Y > * Are you sure that CLK_MM_DPI0_DPI0's parent shouldn't be dpi0_sel > instead? I'm agree with you. After few change, it works. - GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20), + GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20), - clocks = <&topckgen CLK_TOP_DPI0_SEL>, + clocks = <&mmsys CLK_MM_DPI0_DPI0>, enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- vpll_dpix 0 0 0 75000000 0 0 50000 Y mm_flvdstx_pxl 0 0 0 75000000 0 0 50000 N vpll_dpix_en 0 0 0 75000000 0 0 50000 N lvdspll 1 1 0 283999497 0 0 50000 Y lvdspll_d16 0 0 0 17749968 0 0 50000 Y lvdspll_d8 0 0 0 35499937 0 0 50000 Y lvdspll_d4 0 0 0 70999874 0 0 50000 Y lvdspll_d2 1 1 0 141999748 0 0 50000 Y dpi0_sel 1 1 0 141999748 0 0 50000 Y mm_dpi0_dpi0 1 1 0 141999748 0 0 50000 Y dpi1_sel 0 0 0 141999748 0 0 50000 N mmpll 1 1 0 456999909 0 0 50000 Y mmpll_d2 0 0 0 228499954 0 0 50000 Y mmpll_ck 1 1 0 456999909 0 0 50000 Y mm_sel 15 15 0 456999909 0 0 50000 Y mm_dpi0 1 1 0 456999909 0 0 50000 Y > * Where is DPI1 in this SoC? Why is there a dpi1_sel clock, but no MM clock >   for the DPI1 controller? Is there any DPI1 controller, even?! DPI1 isn't documented. >   * Why is there a DPI1 MUX, if there's no DPI1 controller?! Good question, I don't know. Legacy of the downstream code. That will be fixed for the next version. -- Regards, Alexandre